454 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \3; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \4; RUN: FileCheck %s --check-prefix=CHECK-P85; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \6; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \7; RUN: FileCheck %s --check-prefix=CHECK-P98; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \9; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \10; RUN: FileCheck %s --check-prefix=CHECK-BE11 12define i64 @test2elt(i32 %a.coerce) local_unnamed_addr #0 {13; CHECK-P8-LABEL: test2elt:14; CHECK-P8: # %bb.0: # %entry15; CHECK-P8-NEXT: mtfprd f0, r316; CHECK-P8-NEXT: mffprd r3, f017; CHECK-P8-NEXT: clrldi r4, r3, 4818; CHECK-P8-NEXT: rldicl r3, r3, 48, 4819; CHECK-P8-NEXT: clrlwi r4, r4, 1620; CHECK-P8-NEXT: clrlwi r3, r3, 1621; CHECK-P8-NEXT: mtfprwz f0, r422; CHECK-P8-NEXT: mtfprwz f1, r323; CHECK-P8-NEXT: xscvuxdsp f0, f024; CHECK-P8-NEXT: xscvuxdsp f1, f125; CHECK-P8-NEXT: xscvdpspn vs0, f026; CHECK-P8-NEXT: xscvdpspn vs1, f127; CHECK-P8-NEXT: xxmrghw vs0, vs1, vs028; CHECK-P8-NEXT: xxswapd vs0, vs029; CHECK-P8-NEXT: mffprd r3, f030; CHECK-P8-NEXT: blr31;32; CHECK-P9-LABEL: test2elt:33; CHECK-P9: # %bb.0: # %entry34; CHECK-P9-NEXT: mtvsrws v2, r335; CHECK-P9-NEXT: vextractuh v3, v2, 1436; CHECK-P9-NEXT: vextractuh v2, v2, 1237; CHECK-P9-NEXT: xscvuxdsp f0, v338; CHECK-P9-NEXT: xscvuxdsp f1, v239; CHECK-P9-NEXT: xscvdpspn vs0, f040; CHECK-P9-NEXT: xscvdpspn vs1, f141; CHECK-P9-NEXT: xxmrghw vs0, vs1, vs042; CHECK-P9-NEXT: mfvsrld r3, vs043; CHECK-P9-NEXT: blr44;45; CHECK-BE-LABEL: test2elt:46; CHECK-BE: # %bb.0: # %entry47; CHECK-BE-NEXT: mtvsrws v2, r348; CHECK-BE-NEXT: vextractuh v3, v2, 249; CHECK-BE-NEXT: vextractuh v2, v2, 050; CHECK-BE-NEXT: xscvuxdsp f0, v351; CHECK-BE-NEXT: xscvdpspn v3, f052; CHECK-BE-NEXT: xscvuxdsp f0, v253; CHECK-BE-NEXT: xscvdpspn v2, f054; CHECK-BE-NEXT: vmrgow v2, v2, v355; CHECK-BE-NEXT: mfvsrd r3, v256; CHECK-BE-NEXT: blr57entry:58 %0 = bitcast i32 %a.coerce to <2 x i16>59 %1 = uitofp <2 x i16> %0 to <2 x float>60 %2 = bitcast <2 x float> %1 to i6461 ret i64 %262}63 64define <4 x float> @test4elt(i64 %a.coerce) local_unnamed_addr #1 {65; CHECK-P8-LABEL: test4elt:66; CHECK-P8: # %bb.0: # %entry67; CHECK-P8-NEXT: mtvsrd v2, r368; CHECK-P8-NEXT: xxlxor v3, v3, v369; CHECK-P8-NEXT: vmrghh v2, v3, v270; CHECK-P8-NEXT: xvcvuxwsp v2, v271; CHECK-P8-NEXT: blr72;73; CHECK-P9-LABEL: test4elt:74; CHECK-P9: # %bb.0: # %entry75; CHECK-P9-NEXT: mtvsrd v2, r376; CHECK-P9-NEXT: xxlxor v3, v3, v377; CHECK-P9-NEXT: vmrghh v2, v3, v278; CHECK-P9-NEXT: xvcvuxwsp v2, v279; CHECK-P9-NEXT: blr80;81; CHECK-BE-LABEL: test4elt:82; CHECK-BE: # %bb.0: # %entry83; CHECK-BE-NEXT: mtfprd f0, r384; CHECK-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha85; CHECK-BE-NEXT: xxlxor vs2, vs2, vs286; CHECK-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l87; CHECK-BE-NEXT: lxv vs1, 0(r3)88; CHECK-BE-NEXT: xxperm vs0, vs2, vs189; CHECK-BE-NEXT: xvcvuxwsp v2, vs090; CHECK-BE-NEXT: blr91entry:92 %0 = bitcast i64 %a.coerce to <4 x i16>93 %1 = uitofp <4 x i16> %0 to <4 x float>94 ret <4 x float> %195}96 97define void @test8elt(ptr noalias nocapture sret(<8 x float>) %agg.result, <8 x i16> %a) local_unnamed_addr #2 {98; CHECK-P8-LABEL: test8elt:99; CHECK-P8: # %bb.0: # %entry100; CHECK-P8-NEXT: xxlxor v3, v3, v3101; CHECK-P8-NEXT: li r4, 16102; CHECK-P8-NEXT: vmrglh v4, v3, v2103; CHECK-P8-NEXT: vmrghh v2, v3, v2104; CHECK-P8-NEXT: xvcvuxwsp vs0, v4105; CHECK-P8-NEXT: xvcvuxwsp vs1, v2106; CHECK-P8-NEXT: xxswapd vs1, vs1107; CHECK-P8-NEXT: xxswapd vs0, vs0108; CHECK-P8-NEXT: stxvd2x vs1, r3, r4109; CHECK-P8-NEXT: stxvd2x vs0, 0, r3110; CHECK-P8-NEXT: blr111;112; CHECK-P9-LABEL: test8elt:113; CHECK-P9: # %bb.0: # %entry114; CHECK-P9-NEXT: xxlxor v3, v3, v3115; CHECK-P9-NEXT: vmrglh v4, v3, v2116; CHECK-P9-NEXT: vmrghh v2, v3, v2117; CHECK-P9-NEXT: xvcvuxwsp vs0, v4118; CHECK-P9-NEXT: xvcvuxwsp vs1, v2119; CHECK-P9-NEXT: stxv vs1, 16(r3)120; CHECK-P9-NEXT: stxv vs0, 0(r3)121; CHECK-P9-NEXT: blr122;123; CHECK-BE-LABEL: test8elt:124; CHECK-BE: # %bb.0: # %entry125; CHECK-BE-NEXT: xxlxor v3, v3, v3126; CHECK-BE-NEXT: vmrghh v4, v3, v2127; CHECK-BE-NEXT: vmrglh v2, v3, v2128; CHECK-BE-NEXT: xvcvuxwsp vs0, v4129; CHECK-BE-NEXT: xvcvuxwsp vs1, v2130; CHECK-BE-NEXT: stxv vs1, 16(r3)131; CHECK-BE-NEXT: stxv vs0, 0(r3)132; CHECK-BE-NEXT: blr133entry:134 %0 = uitofp <8 x i16> %a to <8 x float>135 store <8 x float> %0, ptr %agg.result, align 32136 ret void137}138 139define void @test16elt(ptr noalias nocapture sret(<16 x float>) %agg.result, ptr nocapture readonly) local_unnamed_addr #3 {140; CHECK-P8-LABEL: test16elt:141; CHECK-P8: # %bb.0: # %entry142; CHECK-P8-NEXT: li r5, 16143; CHECK-P8-NEXT: lxvd2x vs1, 0, r4144; CHECK-P8-NEXT: xxlxor v0, v0, v0145; CHECK-P8-NEXT: lxvd2x vs0, r4, r5146; CHECK-P8-NEXT: addis r4, r2, .LCPI3_1@toc@ha147; CHECK-P8-NEXT: addi r4, r4, .LCPI3_1@toc@l148; CHECK-P8-NEXT: lxvd2x vs2, 0, r4149; CHECK-P8-NEXT: addis r4, r2, .LCPI3_0@toc@ha150; CHECK-P8-NEXT: addi r4, r4, .LCPI3_0@toc@l151; CHECK-P8-NEXT: xxswapd v4, vs1152; CHECK-P8-NEXT: xxswapd v2, vs0153; CHECK-P8-NEXT: lxvd2x vs0, 0, r4154; CHECK-P8-NEXT: li r4, 48155; CHECK-P8-NEXT: xxswapd v3, vs2156; CHECK-P8-NEXT: vperm v1, v0, v2, v3157; CHECK-P8-NEXT: vperm v3, v0, v4, v3158; CHECK-P8-NEXT: xvcvuxwsp vs2, v1159; CHECK-P8-NEXT: xvcvuxwsp vs1, v3160; CHECK-P8-NEXT: xxswapd v5, vs0161; CHECK-P8-NEXT: vperm v4, v0, v4, v5162; CHECK-P8-NEXT: vperm v2, v0, v2, v5163; CHECK-P8-NEXT: xvcvuxwsp vs0, v4164; CHECK-P8-NEXT: xvcvuxwsp vs3, v2165; CHECK-P8-NEXT: xxswapd vs2, vs2166; CHECK-P8-NEXT: xxswapd vs1, vs1167; CHECK-P8-NEXT: stxvd2x vs2, r3, r4168; CHECK-P8-NEXT: li r4, 32169; CHECK-P8-NEXT: stxvd2x vs1, r3, r5170; CHECK-P8-NEXT: xxswapd vs3, vs3171; CHECK-P8-NEXT: xxswapd vs0, vs0172; CHECK-P8-NEXT: stxvd2x vs3, r3, r4173; CHECK-P8-NEXT: stxvd2x vs0, 0, r3174; CHECK-P8-NEXT: blr175;176; CHECK-P9-LABEL: test16elt:177; CHECK-P9: # %bb.0: # %entry178; CHECK-P9-NEXT: lxv v2, 16(r4)179; CHECK-P9-NEXT: lxv v3, 0(r4)180; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha181; CHECK-P9-NEXT: xxlxor v5, v5, v5182; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l183; CHECK-P9-NEXT: lxv v4, 0(r4)184; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha185; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l186; CHECK-P9-NEXT: vperm v0, v5, v3, v4187; CHECK-P9-NEXT: xvcvuxwsp vs0, v0188; CHECK-P9-NEXT: lxv v0, 0(r4)189; CHECK-P9-NEXT: vperm v3, v5, v3, v0190; CHECK-P9-NEXT: stxv vs0, 0(r3)191; CHECK-P9-NEXT: xvcvuxwsp vs1, v3192; CHECK-P9-NEXT: vperm v3, v5, v2, v4193; CHECK-P9-NEXT: vperm v2, v5, v2, v0194; CHECK-P9-NEXT: xvcvuxwsp vs2, v3195; CHECK-P9-NEXT: xvcvuxwsp vs3, v2196; CHECK-P9-NEXT: stxv vs1, 16(r3)197; CHECK-P9-NEXT: stxv vs3, 48(r3)198; CHECK-P9-NEXT: stxv vs2, 32(r3)199; CHECK-P9-NEXT: blr200;201; CHECK-BE-LABEL: test16elt:202; CHECK-BE: # %bb.0: # %entry203; CHECK-BE-NEXT: lxv v2, 16(r4)204; CHECK-BE-NEXT: lxv v3, 0(r4)205; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha206; CHECK-BE-NEXT: xxlxor v5, v5, v5207; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l208; CHECK-BE-NEXT: lxv v4, 0(r4)209; CHECK-BE-NEXT: vperm v0, v5, v3, v4210; CHECK-BE-NEXT: vperm v4, v5, v2, v4211; CHECK-BE-NEXT: vmrglh v3, v5, v3212; CHECK-BE-NEXT: vmrglh v2, v5, v2213; CHECK-BE-NEXT: xvcvuxwsp vs0, v0214; CHECK-BE-NEXT: xvcvuxwsp vs1, v4215; CHECK-BE-NEXT: stxv vs1, 32(r3)216; CHECK-BE-NEXT: xvcvuxwsp vs2, v3217; CHECK-BE-NEXT: xvcvuxwsp vs3, v2218; CHECK-BE-NEXT: stxv vs3, 48(r3)219; CHECK-BE-NEXT: stxv vs2, 16(r3)220; CHECK-BE-NEXT: stxv vs0, 0(r3)221; CHECK-BE-NEXT: blr222entry:223 %a = load <16 x i16>, ptr %0, align 32224 %1 = uitofp <16 x i16> %a to <16 x float>225 store <16 x float> %1, ptr %agg.result, align 64226 ret void227}228 229define i64 @test2elt_signed(i32 %a.coerce) local_unnamed_addr #0 {230; CHECK-P8-LABEL: test2elt_signed:231; CHECK-P8: # %bb.0: # %entry232; CHECK-P8-NEXT: mtfprd f0, r3233; CHECK-P8-NEXT: mffprd r3, f0234; CHECK-P8-NEXT: clrldi r4, r3, 48235; CHECK-P8-NEXT: rldicl r3, r3, 48, 48236; CHECK-P8-NEXT: extsh r4, r4237; CHECK-P8-NEXT: extsh r3, r3238; CHECK-P8-NEXT: mtfprwa f0, r4239; CHECK-P8-NEXT: mtfprwa f1, r3240; CHECK-P8-NEXT: xscvsxdsp f0, f0241; CHECK-P8-NEXT: xscvsxdsp f1, f1242; CHECK-P8-NEXT: xscvdpspn vs0, f0243; CHECK-P8-NEXT: xscvdpspn vs1, f1244; CHECK-P8-NEXT: xxmrghw vs0, vs1, vs0245; CHECK-P8-NEXT: xxswapd vs0, vs0246; CHECK-P8-NEXT: mffprd r3, f0247; CHECK-P8-NEXT: blr248;249; CHECK-P9-LABEL: test2elt_signed:250; CHECK-P9: # %bb.0: # %entry251; CHECK-P9-NEXT: mtvsrws v2, r3252; CHECK-P9-NEXT: vextractuh v3, v2, 14253; CHECK-P9-NEXT: vextractuh v2, v2, 12254; CHECK-P9-NEXT: vextsh2d v3, v3255; CHECK-P9-NEXT: vextsh2d v2, v2256; CHECK-P9-NEXT: xscvsxdsp f0, v3257; CHECK-P9-NEXT: xscvsxdsp f1, v2258; CHECK-P9-NEXT: xscvdpspn vs0, f0259; CHECK-P9-NEXT: xscvdpspn vs1, f1260; CHECK-P9-NEXT: xxmrghw vs0, vs1, vs0261; CHECK-P9-NEXT: mfvsrld r3, vs0262; CHECK-P9-NEXT: blr263;264; CHECK-BE-LABEL: test2elt_signed:265; CHECK-BE: # %bb.0: # %entry266; CHECK-BE-NEXT: mtvsrws v2, r3267; CHECK-BE-NEXT: vextractuh v3, v2, 2268; CHECK-BE-NEXT: vextractuh v2, v2, 0269; CHECK-BE-NEXT: vextsh2d v3, v3270; CHECK-BE-NEXT: vextsh2d v2, v2271; CHECK-BE-NEXT: xscvsxdsp f0, v3272; CHECK-BE-NEXT: xscvdpspn v3, f0273; CHECK-BE-NEXT: xscvsxdsp f0, v2274; CHECK-BE-NEXT: xscvdpspn v2, f0275; CHECK-BE-NEXT: vmrgow v2, v2, v3276; CHECK-BE-NEXT: mfvsrd r3, v2277; CHECK-BE-NEXT: blr278entry:279 %0 = bitcast i32 %a.coerce to <2 x i16>280 %1 = sitofp <2 x i16> %0 to <2 x float>281 %2 = bitcast <2 x float> %1 to i64282 ret i64 %2283}284 285define <4 x float> @test4elt_signed(i64 %a.coerce) local_unnamed_addr #1 {286; CHECK-P8-LABEL: test4elt_signed:287; CHECK-P8: # %bb.0: # %entry288; CHECK-P8-NEXT: mtvsrd v3, r3289; CHECK-P8-NEXT: vspltisw v2, 8290; CHECK-P8-NEXT: vadduwm v2, v2, v2291; CHECK-P8-NEXT: vmrghh v3, v3, v3292; CHECK-P8-NEXT: vslw v3, v3, v2293; CHECK-P8-NEXT: vsraw v2, v3, v2294; CHECK-P8-NEXT: xvcvsxwsp v2, v2295; CHECK-P8-NEXT: blr296;297; CHECK-P9-LABEL: test4elt_signed:298; CHECK-P9: # %bb.0: # %entry299; CHECK-P9-NEXT: mtvsrd v2, r3300; CHECK-P9-NEXT: vmrghh v2, v2, v2301; CHECK-P9-NEXT: vextsh2w v2, v2302; CHECK-P9-NEXT: xvcvsxwsp v2, v2303; CHECK-P9-NEXT: blr304;305; CHECK-BE-LABEL: test4elt_signed:306; CHECK-BE: # %bb.0: # %entry307; CHECK-BE-NEXT: mtvsrd v2, r3308; CHECK-BE-NEXT: vmrghh v2, v2, v2309; CHECK-BE-NEXT: vextsh2w v2, v2310; CHECK-BE-NEXT: xvcvsxwsp v2, v2311; CHECK-BE-NEXT: blr312entry:313 %0 = bitcast i64 %a.coerce to <4 x i16>314 %1 = sitofp <4 x i16> %0 to <4 x float>315 ret <4 x float> %1316}317 318define void @test8elt_signed(ptr noalias nocapture sret(<8 x float>) %agg.result, <8 x i16> %a) local_unnamed_addr #2 {319; CHECK-P8-LABEL: test8elt_signed:320; CHECK-P8: # %bb.0: # %entry321; CHECK-P8-NEXT: vspltisw v3, 8322; CHECK-P8-NEXT: vmrglh v4, v2, v2323; CHECK-P8-NEXT: li r4, 16324; CHECK-P8-NEXT: vadduwm v3, v3, v3325; CHECK-P8-NEXT: vmrghh v2, v2, v2326; CHECK-P8-NEXT: vslw v4, v4, v3327; CHECK-P8-NEXT: vslw v2, v2, v3328; CHECK-P8-NEXT: vsraw v4, v4, v3329; CHECK-P8-NEXT: vsraw v2, v2, v3330; CHECK-P8-NEXT: xvcvsxwsp vs0, v4331; CHECK-P8-NEXT: xvcvsxwsp vs1, v2332; CHECK-P8-NEXT: xxswapd vs1, vs1333; CHECK-P8-NEXT: xxswapd vs0, vs0334; CHECK-P8-NEXT: stxvd2x vs1, r3, r4335; CHECK-P8-NEXT: stxvd2x vs0, 0, r3336; CHECK-P8-NEXT: blr337;338; CHECK-P9-LABEL: test8elt_signed:339; CHECK-P9: # %bb.0: # %entry340; CHECK-P9-NEXT: vmrglh v3, v2, v2341; CHECK-P9-NEXT: vmrghh v2, v2, v2342; CHECK-P9-NEXT: vextsh2w v3, v3343; CHECK-P9-NEXT: vextsh2w v2, v2344; CHECK-P9-NEXT: xvcvsxwsp vs0, v3345; CHECK-P9-NEXT: xvcvsxwsp vs1, v2346; CHECK-P9-NEXT: stxv vs1, 16(r3)347; CHECK-P9-NEXT: stxv vs0, 0(r3)348; CHECK-P9-NEXT: blr349;350; CHECK-BE-LABEL: test8elt_signed:351; CHECK-BE: # %bb.0: # %entry352; CHECK-BE-NEXT: vmrghh v3, v2, v2353; CHECK-BE-NEXT: vmrglh v2, v2, v2354; CHECK-BE-NEXT: vextsh2w v3, v3355; CHECK-BE-NEXT: vextsh2w v2, v2356; CHECK-BE-NEXT: xvcvsxwsp vs0, v3357; CHECK-BE-NEXT: xvcvsxwsp vs1, v2358; CHECK-BE-NEXT: stxv vs1, 16(r3)359; CHECK-BE-NEXT: stxv vs0, 0(r3)360; CHECK-BE-NEXT: blr361entry:362 %0 = sitofp <8 x i16> %a to <8 x float>363 store <8 x float> %0, ptr %agg.result, align 32364 ret void365}366 367define void @test16elt_signed(ptr noalias nocapture sret(<16 x float>) %agg.result, ptr nocapture readonly) local_unnamed_addr #3 {368; CHECK-P8-LABEL: test16elt_signed:369; CHECK-P8: # %bb.0: # %entry370; CHECK-P8-NEXT: li r5, 16371; CHECK-P8-NEXT: vspltisw v2, 8372; CHECK-P8-NEXT: lxvd2x vs0, r4, r5373; CHECK-P8-NEXT: vadduwm v2, v2, v2374; CHECK-P8-NEXT: xxswapd v3, vs0375; CHECK-P8-NEXT: lxvd2x vs0, 0, r4376; CHECK-P8-NEXT: li r4, 48377; CHECK-P8-NEXT: vmrghh v5, v3, v3378; CHECK-P8-NEXT: vmrglh v3, v3, v3379; CHECK-P8-NEXT: vslw v3, v3, v2380; CHECK-P8-NEXT: vslw v5, v5, v2381; CHECK-P8-NEXT: vsraw v3, v3, v2382; CHECK-P8-NEXT: xvcvsxwsp vs3, v3383; CHECK-P8-NEXT: xxswapd v4, vs0384; CHECK-P8-NEXT: vmrglh v0, v4, v4385; CHECK-P8-NEXT: vmrghh v4, v4, v4386; CHECK-P8-NEXT: vslw v0, v0, v2387; CHECK-P8-NEXT: vslw v4, v4, v2388; CHECK-P8-NEXT: vsraw v0, v0, v2389; CHECK-P8-NEXT: vsraw v4, v4, v2390; CHECK-P8-NEXT: vsraw v2, v5, v2391; CHECK-P8-NEXT: xvcvsxwsp vs2, v2392; CHECK-P8-NEXT: xvcvsxwsp vs0, v0393; CHECK-P8-NEXT: xvcvsxwsp vs1, v4394; CHECK-P8-NEXT: xxswapd vs3, vs3395; CHECK-P8-NEXT: xxswapd vs2, vs2396; CHECK-P8-NEXT: xxswapd vs1, vs1397; CHECK-P8-NEXT: xxswapd vs0, vs0398; CHECK-P8-NEXT: stxvd2x vs2, r3, r4399; CHECK-P8-NEXT: li r4, 32400; CHECK-P8-NEXT: stxvd2x vs1, r3, r5401; CHECK-P8-NEXT: stxvd2x vs0, 0, r3402; CHECK-P8-NEXT: stxvd2x vs3, r3, r4403; CHECK-P8-NEXT: blr404;405; CHECK-P9-LABEL: test16elt_signed:406; CHECK-P9: # %bb.0: # %entry407; CHECK-P9-NEXT: lxv v3, 0(r4)408; CHECK-P9-NEXT: lxv v2, 16(r4)409; CHECK-P9-NEXT: vmrglh v4, v3, v3410; CHECK-P9-NEXT: vmrghh v3, v3, v3411; CHECK-P9-NEXT: vextsh2w v3, v3412; CHECK-P9-NEXT: vextsh2w v4, v4413; CHECK-P9-NEXT: xvcvsxwsp vs1, v3414; CHECK-P9-NEXT: vmrglh v3, v2, v2415; CHECK-P9-NEXT: vmrghh v2, v2, v2416; CHECK-P9-NEXT: xvcvsxwsp vs0, v4417; CHECK-P9-NEXT: vextsh2w v3, v3418; CHECK-P9-NEXT: vextsh2w v2, v2419; CHECK-P9-NEXT: xvcvsxwsp vs2, v3420; CHECK-P9-NEXT: xvcvsxwsp vs3, v2421; CHECK-P9-NEXT: stxv vs1, 16(r3)422; CHECK-P9-NEXT: stxv vs0, 0(r3)423; CHECK-P9-NEXT: stxv vs3, 48(r3)424; CHECK-P9-NEXT: stxv vs2, 32(r3)425; CHECK-P9-NEXT: blr426;427; CHECK-BE-LABEL: test16elt_signed:428; CHECK-BE: # %bb.0: # %entry429; CHECK-BE-NEXT: lxv v3, 0(r4)430; CHECK-BE-NEXT: lxv v2, 16(r4)431; CHECK-BE-NEXT: vmrghh v4, v3, v3432; CHECK-BE-NEXT: vmrglh v3, v3, v3433; CHECK-BE-NEXT: vextsh2w v3, v3434; CHECK-BE-NEXT: vextsh2w v4, v4435; CHECK-BE-NEXT: xvcvsxwsp vs1, v3436; CHECK-BE-NEXT: vmrghh v3, v2, v2437; CHECK-BE-NEXT: vmrglh v2, v2, v2438; CHECK-BE-NEXT: xvcvsxwsp vs0, v4439; CHECK-BE-NEXT: vextsh2w v3, v3440; CHECK-BE-NEXT: vextsh2w v2, v2441; CHECK-BE-NEXT: xvcvsxwsp vs2, v3442; CHECK-BE-NEXT: xvcvsxwsp vs3, v2443; CHECK-BE-NEXT: stxv vs1, 16(r3)444; CHECK-BE-NEXT: stxv vs0, 0(r3)445; CHECK-BE-NEXT: stxv vs3, 48(r3)446; CHECK-BE-NEXT: stxv vs2, 32(r3)447; CHECK-BE-NEXT: blr448entry:449 %a = load <16 x i16>, ptr %0, align 32450 %1 = sitofp <16 x i16> %a to <16 x float>451 store <16 x float> %1, ptr %agg.result, align 64452 ret void453}454