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1; RUN: llc -verify-machineinstrs -mcpu=pwr6 -mattr=+altivec -code-model=small < %s | FileCheck %s2 3; Check vector extend load expansion with altivec enabled.4 5target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"6target triple = "powerpc64-unknown-linux-gnu"7 8; Altivec does not provides an sext instruction, so it expands9; a set of vector stores (stvx), bytes load/sign expand/store10; (lbz/stb), and a final vector load (lvx) to load the result11; extended vector.12define <16 x i8> @v16si8_sext_in_reg(<16 x i8> %a) {13 %b = trunc <16 x i8> %a to <16 x i4>14 %c = sext <16 x i4> %b to <16 x i8>15 ret <16 x i8> %c16}17; CHECK-LABEL: v16si8_sext_in_reg:18; CHECK: vslb19; CHECK: vsrab20; CHECK: blr 21 22; The zero extend uses a more clever logic: a vector splat23; and a logic and to set higher bits to 0.24define <16 x i8> @v16si8_zext_in_reg(<16 x i8> %a) {25 %b = trunc <16 x i8> %a to <16 x i4>26 %c = zext <16 x i4> %b to <16 x i8>27 ret <16 x i8> %c28}29; CHECK-LABEL: v16si8_zext_in_reg:30; CHECK: vspltisb [[VMASK:[0-9]+]], 1531; CHECK-NEXT: vand 2, 2, [[VMASK]]32 33; Same as v16si8_sext_in_reg, expands to load/store halfwords (lhz/sth).34define <8 x i16> @v8si16_sext_in_reg(<8 x i16> %a) {35 %b = trunc <8 x i16> %a to <8 x i8>36 %c = sext <8 x i8> %b to <8 x i16>37 ret <8 x i16> %c38}39; CHECK-LABEL: v8si16_sext_in_reg:40; CHECK: vslh41; CHECK: vsrah42; CHECK: blr 43 44; Same as v8si16_sext_in_reg, but instead of creating the mask45; with a splat, loads it from memory.46define <8 x i16> @v8si16_zext_in_reg(<8 x i16> %a) {47 %b = trunc <8 x i16> %a to <8 x i8>48 %c = zext <8 x i8> %b to <8 x i16>49 ret <8 x i16> %c50}51; CHECK-LABEL: v8si16_zext_in_reg:52; CHECK: ld [[RMASKTOC:[0-9]+]], .LC{{[0-9]+}}@toc(2)53; CHECK-NEXT: lvx [[VMASK:[0-9]+]], {{[0-9]+}}, [[RMASKTOC]]54; CHECK-NEXT: vand 2, 2, [[VMASK]]55 56; Same as v16si8_sext_in_reg, expands to load halfword (lha) and57; store words (stw).58define <4 x i32> @v4si32_sext_in_reg(<4 x i32> %a) {59 %b = trunc <4 x i32> %a to <4 x i16>60 %c = sext <4 x i16> %b to <4 x i32>61 ret <4 x i32> %c62}63; CHECK-LABEL: v4si32_sext_in_reg:64; CHECK: vslw65; CHECK: vsraw66; CHECK: blr 67 68; Same as v8si16_sext_in_reg.69define <4 x i32> @v4si32_zext_in_reg(<4 x i32> %a) {70 %b = trunc <4 x i32> %a to <4 x i16>71 %c = zext <4 x i16> %b to <4 x i32>72 ret <4 x i32> %c73}74; CHECK-LABEL: v4si32_zext_in_reg:75; CHECK: vspltisw [[VMASK:[0-9]+]], -1676; CHECK-NEXT: vsrw [[VMASK]], [[VMASK]], [[VMASK]]77; CHECK-NEXT: vand 2, 2, [[VMASK]]78