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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-LE3; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-BE4 5define zeroext i8 @test1(<16 x i8> %a, i32 signext %index) {6; CHECK-LE-LABEL: test1:7; CHECK-LE:       # %bb.0: # %entry8; CHECK-LE-NEXT:    clrldi 3, 5, 329; CHECK-LE-NEXT:    vextubrx 3, 3, 210; CHECK-LE-NEXT:    clrldi 3, 3, 5611; CHECK-LE-NEXT:    blr12;13; CHECK-BE-LABEL: test1:14; CHECK-BE:       # %bb.0: # %entry15; CHECK-BE-NEXT:    clrldi 3, 5, 3216; CHECK-BE-NEXT:    vextublx 3, 3, 217; CHECK-BE-NEXT:    clrldi 3, 3, 5618; CHECK-BE-NEXT:    blr19 20entry:21  %vecext = extractelement <16 x i8> %a, i32 %index22  ret i8 %vecext23}24 25define signext i8 @test2(<16 x i8> %a, i32 signext %index) {26; CHECK-LE-LABEL: test2:27; CHECK-LE:       # %bb.0: # %entry28; CHECK-LE-NEXT:    clrldi 3, 5, 3229; CHECK-LE-NEXT:    vextubrx 3, 3, 230; CHECK-LE-NEXT:    extsb 3, 331; CHECK-LE-NEXT:    blr32;33; CHECK-BE-LABEL: test2:34; CHECK-BE:       # %bb.0: # %entry35; CHECK-BE-NEXT:    clrldi 3, 5, 3236; CHECK-BE-NEXT:    vextublx 3, 3, 237; CHECK-BE-NEXT:    extsb 3, 338; CHECK-BE-NEXT:    blr39 40entry:41  %vecext = extractelement <16 x i8> %a, i32 %index42  ret i8 %vecext43}44 45define zeroext i16 @test3(<8 x i16> %a, i32 signext %index) {46; CHECK-LE-LABEL: test3:47; CHECK-LE:       # %bb.0: # %entry48; CHECK-LE-NEXT:    clrldi 3, 5, 3249; CHECK-LE-NEXT:    rlwinm 3, 3, 1, 28, 3050; CHECK-LE-NEXT:    vextuhrx 3, 3, 251; CHECK-LE-NEXT:    clrldi 3, 3, 4852; CHECK-LE-NEXT:    blr53;54; CHECK-BE-LABEL: test3:55; CHECK-BE:       # %bb.0: # %entry56; CHECK-BE-NEXT:    clrldi 3, 5, 3257; CHECK-BE-NEXT:    rlwinm 3, 3, 1, 28, 3058; CHECK-BE-NEXT:    vextuhlx 3, 3, 259; CHECK-BE-NEXT:    clrldi 3, 3, 4860; CHECK-BE-NEXT:    blr61 62entry:63  %vecext = extractelement <8 x i16> %a, i32 %index64  ret i16 %vecext65}66 67define signext i16 @test4(<8 x i16> %a, i32 signext %index) {68; CHECK-LE-LABEL: test4:69; CHECK-LE:       # %bb.0: # %entry70; CHECK-LE-NEXT:    clrldi 3, 5, 3271; CHECK-LE-NEXT:    rlwinm 3, 3, 1, 28, 3072; CHECK-LE-NEXT:    vextuhrx 3, 3, 273; CHECK-LE-NEXT:    extsh 3, 374; CHECK-LE-NEXT:    blr75;76; CHECK-BE-LABEL: test4:77; CHECK-BE:       # %bb.0: # %entry78; CHECK-BE-NEXT:    clrldi 3, 5, 3279; CHECK-BE-NEXT:    rlwinm 3, 3, 1, 28, 3080; CHECK-BE-NEXT:    vextuhlx 3, 3, 281; CHECK-BE-NEXT:    extsh 3, 382; CHECK-BE-NEXT:    blr83 84entry:85  %vecext = extractelement <8 x i16> %a, i32 %index86  ret i16 %vecext87}88 89define zeroext i32 @test5(<4 x i32> %a, i32 signext %index) {90; CHECK-LE-LABEL: test5:91; CHECK-LE:       # %bb.0: # %entry92; CHECK-LE-NEXT:    clrldi 3, 5, 3293; CHECK-LE-NEXT:    rlwinm 3, 3, 2, 28, 2994; CHECK-LE-NEXT:    vextuwrx 3, 3, 295; CHECK-LE-NEXT:    blr96;97; CHECK-BE-LABEL: test5:98; CHECK-BE:       # %bb.0: # %entry99; CHECK-BE-NEXT:    clrldi 3, 5, 32100; CHECK-BE-NEXT:    rlwinm 3, 3, 2, 28, 29101; CHECK-BE-NEXT:    vextuwlx 3, 3, 2102; CHECK-BE-NEXT:    blr103 104entry:105  %vecext = extractelement <4 x i32> %a, i32 %index106  ret i32 %vecext107}108 109define signext i32 @test6(<4 x i32> %a, i32 signext %index) {110; CHECK-LE-LABEL: test6:111; CHECK-LE:       # %bb.0: # %entry112; CHECK-LE-NEXT:    clrldi 3, 5, 32113; CHECK-LE-NEXT:    rlwinm 3, 3, 2, 28, 29114; CHECK-LE-NEXT:    vextuwrx 3, 3, 2115; CHECK-LE-NEXT:    extsw 3, 3116; CHECK-LE-NEXT:    blr117;118; CHECK-BE-LABEL: test6:119; CHECK-BE:       # %bb.0: # %entry120; CHECK-BE-NEXT:    clrldi 3, 5, 32121; CHECK-BE-NEXT:    rlwinm 3, 3, 2, 28, 29122; CHECK-BE-NEXT:    vextuwlx 3, 3, 2123; CHECK-BE-NEXT:    extsw 3, 3124; CHECK-BE-NEXT:    blr125 126entry:127  %vecext = extractelement <4 x i32> %a, i32 %index128  ret i32 %vecext129}130 131; Test with immediate index132define zeroext i8 @test7(<16 x i8> %a) {133; CHECK-LE-LABEL: test7:134; CHECK-LE:       # %bb.0: # %entry135; CHECK-LE-NEXT:    li 3, 1136; CHECK-LE-NEXT:    vextubrx 3, 3, 2137; CHECK-LE-NEXT:    clrldi 3, 3, 56138; CHECK-LE-NEXT:    blr139;140; CHECK-BE-LABEL: test7:141; CHECK-BE:       # %bb.0: # %entry142; CHECK-BE-NEXT:    li 3, 1143; CHECK-BE-NEXT:    vextublx 3, 3, 2144; CHECK-BE-NEXT:    clrldi 3, 3, 56145; CHECK-BE-NEXT:    blr146 147entry:148  %vecext = extractelement <16 x i8> %a, i32 1149  ret i8 %vecext150}151 152define zeroext i16 @test8(<8 x i16> %a) {153; CHECK-LE-LABEL: test8:154; CHECK-LE:       # %bb.0: # %entry155; CHECK-LE-NEXT:    li 3, 2156; CHECK-LE-NEXT:    vextuhrx 3, 3, 2157; CHECK-LE-NEXT:    clrldi 3, 3, 48158; CHECK-LE-NEXT:    blr159;160; CHECK-BE-LABEL: test8:161; CHECK-BE:       # %bb.0: # %entry162; CHECK-BE-NEXT:    li 3, 2163; CHECK-BE-NEXT:    vextuhlx 3, 3, 2164; CHECK-BE-NEXT:    clrldi 3, 3, 48165; CHECK-BE-NEXT:    blr166 167entry:168  %vecext = extractelement <8 x i16> %a, i32 1169  ret i16 %vecext170}171 172define zeroext i32 @test9(<4 x i32> %a) {173; CHECK-LE-LABEL: test9:174; CHECK-LE:       # %bb.0: # %entry175; CHECK-LE-NEXT:    li 3, 12176; CHECK-LE-NEXT:    vextuwrx 3, 3, 2177; CHECK-LE-NEXT:    blr178;179; CHECK-BE-LABEL: test9:180; CHECK-BE:       # %bb.0: # %entry181; CHECK-BE-NEXT:    li 3, 12182; CHECK-BE-NEXT:    vextuwlx 3, 3, 2183; CHECK-BE-NEXT:    blr184 185entry:186  %vecext = extractelement <4 x i32> %a, i32 3187  ret i32 %vecext188}189 190define double @test10(<4 x i32> %a, <4 x i32> %b) {191; CHECK-LE-LABEL: test10:192; CHECK-LE:       # %bb.0: # %entry193; CHECK-LE-NEXT:    addis 3, 2, .LCPI9_0@toc@ha194; CHECK-LE-NEXT:    addi 3, 3, .LCPI9_0@toc@l195; CHECK-LE-NEXT:    lxv 0, 0(3)196; CHECK-LE-NEXT:    xxperm 35, 34, 0197; CHECK-LE-NEXT:    vspltisw 2, 1198; CHECK-LE-NEXT:    xvcvsxwdp 1, 34199; CHECK-LE-NEXT:    xxswapd 0, 35200; CHECK-LE-NEXT:    xsadddp 1, 0, 1201; CHECK-LE-NEXT:    blr202;203; CHECK-BE-LABEL: test10:204; CHECK-BE:       # %bb.0: # %entry205; CHECK-BE-NEXT:    addis 3, 2, .LCPI9_0@toc@ha206; CHECK-BE-NEXT:    addi 3, 3, .LCPI9_0@toc@l207; CHECK-BE-NEXT:    lxv 0, 0(3)208; CHECK-BE-NEXT:    xxperm 34, 35, 0209; CHECK-BE-NEXT:    vspltisw 3, 1210; CHECK-BE-NEXT:    xvcvsxwdp 0, 35211; CHECK-BE-NEXT:    xsadddp 1, 34, 0212; CHECK-BE-NEXT:    blr213entry:214  %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 5, i32 2, i32 3, i32 7>215  %cast = bitcast <4 x i32> %shuffle to <2 x double>216  %extract = extractelement <2 x double> %cast, i32 0217  %add = fadd double %extract, 1.0000218  ret double %add219}220