273 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-LE3; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-BE4 5define zeroext i8 @test_add1(<16 x i8> %a, i32 signext %index, i8 zeroext %c) {6; CHECK-LE-LABEL: test_add1:7; CHECK-LE: # %bb.0: # %entry8; CHECK-LE-NEXT: clrldi 3, 5, 329; CHECK-LE-NEXT: vextubrx 3, 3, 210; CHECK-LE-NEXT: add 3, 3, 611; CHECK-LE-NEXT: clrldi 3, 3, 5612; CHECK-LE-NEXT: blr13;14; CHECK-BE-LABEL: test_add1:15; CHECK-BE: # %bb.0: # %entry16; CHECK-BE-NEXT: clrldi 3, 5, 3217; CHECK-BE-NEXT: vextublx 3, 3, 218; CHECK-BE-NEXT: add 3, 3, 619; CHECK-BE-NEXT: clrldi 3, 3, 5620; CHECK-BE-NEXT: blr21entry:22 %vecext = extractelement <16 x i8> %a, i32 %index23 %conv = zext i8 %vecext to i3224 %conv1 = zext i8 %c to i3225 %add = add nuw nsw i32 %conv, %conv126 %conv2 = trunc i32 %add to i827 ret i8 %conv228}29 30define signext i8 @test_add2(<16 x i8> %a, i32 signext %index, i8 signext %c) {31; CHECK-LE-LABEL: test_add2:32; CHECK-LE: # %bb.0: # %entry33; CHECK-LE-NEXT: clrldi 3, 5, 3234; CHECK-LE-NEXT: vextubrx 3, 3, 235; CHECK-LE-NEXT: add 3, 3, 636; CHECK-LE-NEXT: extsb 3, 337; CHECK-LE-NEXT: blr38;39; CHECK-BE-LABEL: test_add2:40; CHECK-BE: # %bb.0: # %entry41; CHECK-BE-NEXT: clrldi 3, 5, 3242; CHECK-BE-NEXT: vextublx 3, 3, 243; CHECK-BE-NEXT: add 3, 3, 644; CHECK-BE-NEXT: extsb 3, 345; CHECK-BE-NEXT: blr46entry:47 %vecext = extractelement <16 x i8> %a, i32 %index48 %conv3 = zext i8 %vecext to i3249 %conv14 = zext i8 %c to i3250 %add = add nuw nsw i32 %conv3, %conv1451 %conv2 = trunc i32 %add to i852 ret i8 %conv253}54 55define zeroext i16 @test_add3(<8 x i16> %a, i32 signext %index, i16 zeroext %c) {56; CHECK-LE-LABEL: test_add3:57; CHECK-LE: # %bb.0: # %entry58; CHECK-LE-NEXT: clrldi 3, 5, 3259; CHECK-LE-NEXT: rlwinm 3, 3, 1, 28, 3060; CHECK-LE-NEXT: vextuhrx 3, 3, 261; CHECK-LE-NEXT: add 3, 3, 662; CHECK-LE-NEXT: clrldi 3, 3, 4863; CHECK-LE-NEXT: blr64;65; CHECK-BE-LABEL: test_add3:66; CHECK-BE: # %bb.0: # %entry67; CHECK-BE-NEXT: clrldi 3, 5, 3268; CHECK-BE-NEXT: rlwinm 3, 3, 1, 28, 3069; CHECK-BE-NEXT: vextuhlx 3, 3, 270; CHECK-BE-NEXT: add 3, 3, 671; CHECK-BE-NEXT: clrldi 3, 3, 4872; CHECK-BE-NEXT: blr73entry:74 %vecext = extractelement <8 x i16> %a, i32 %index75 %conv = zext i16 %vecext to i3276 %conv1 = zext i16 %c to i3277 %add = add nuw nsw i32 %conv, %conv178 %conv2 = trunc i32 %add to i1679 ret i16 %conv280}81 82define signext i16 @test_add4(<8 x i16> %a, i32 signext %index, i16 signext %c) {83; CHECK-LE-LABEL: test_add4:84; CHECK-LE: # %bb.0: # %entry85; CHECK-LE-NEXT: clrldi 3, 5, 3286; CHECK-LE-NEXT: rlwinm 3, 3, 1, 28, 3087; CHECK-LE-NEXT: vextuhrx 3, 3, 288; CHECK-LE-NEXT: add 3, 3, 689; CHECK-LE-NEXT: extsh 3, 390; CHECK-LE-NEXT: blr91;92; CHECK-BE-LABEL: test_add4:93; CHECK-BE: # %bb.0: # %entry94; CHECK-BE-NEXT: clrldi 3, 5, 3295; CHECK-BE-NEXT: rlwinm 3, 3, 1, 28, 3096; CHECK-BE-NEXT: vextuhlx 3, 3, 297; CHECK-BE-NEXT: add 3, 3, 698; CHECK-BE-NEXT: extsh 3, 399; CHECK-BE-NEXT: blr100entry:101 %vecext = extractelement <8 x i16> %a, i32 %index102 %conv5 = zext i16 %vecext to i32103 %conv16 = zext i16 %c to i32104 %add = add nuw nsw i32 %conv5, %conv16105 %conv2 = trunc i32 %add to i16106 ret i16 %conv2107}108 109define zeroext i32 @test_add5(<4 x i32> %a, i32 signext %index, i32 zeroext %c) {110; CHECK-LE-LABEL: test_add5:111; CHECK-LE: # %bb.0: # %entry112; CHECK-LE-NEXT: clrldi 3, 5, 32113; CHECK-LE-NEXT: rlwinm 3, 3, 2, 28, 29114; CHECK-LE-NEXT: vextuwrx 3, 3, 2115; CHECK-LE-NEXT: add 3, 3, 6116; CHECK-LE-NEXT: clrldi 3, 3, 32117; CHECK-LE-NEXT: blr118;119; CHECK-BE-LABEL: test_add5:120; CHECK-BE: # %bb.0: # %entry121; CHECK-BE-NEXT: clrldi 3, 5, 32122; CHECK-BE-NEXT: rlwinm 3, 3, 2, 28, 29123; CHECK-BE-NEXT: vextuwlx 3, 3, 2124; CHECK-BE-NEXT: add 3, 3, 6125; CHECK-BE-NEXT: clrldi 3, 3, 32126; CHECK-BE-NEXT: blr127entry:128 %vecext = extractelement <4 x i32> %a, i32 %index129 %add = add i32 %vecext, %c130 ret i32 %add131}132 133define signext i32 @test_add6(<4 x i32> %a, i32 signext %index, i32 signext %c) {134; CHECK-LE-LABEL: test_add6:135; CHECK-LE: # %bb.0: # %entry136; CHECK-LE-NEXT: clrldi 3, 5, 32137; CHECK-LE-NEXT: rlwinm 3, 3, 2, 28, 29138; CHECK-LE-NEXT: vextuwrx 3, 3, 2139; CHECK-LE-NEXT: add 3, 3, 6140; CHECK-LE-NEXT: extsw 3, 3141; CHECK-LE-NEXT: blr142;143; CHECK-BE-LABEL: test_add6:144; CHECK-BE: # %bb.0: # %entry145; CHECK-BE-NEXT: clrldi 3, 5, 32146; CHECK-BE-NEXT: rlwinm 3, 3, 2, 28, 29147; CHECK-BE-NEXT: vextuwlx 3, 3, 2148; CHECK-BE-NEXT: add 3, 3, 6149; CHECK-BE-NEXT: extsw 3, 3150; CHECK-BE-NEXT: blr151entry:152 %vecext = extractelement <4 x i32> %a, i32 %index153 %add = add nsw i32 %vecext, %c154 ret i32 %add155}156 157; When extracting word element 2 on LE, it's better to use mfvsrwz rather than vextuwrx158define zeroext i32 @test7(<4 x i32> %a) {159; CHECK-LE-LABEL: test7:160; CHECK-LE: # %bb.0: # %entry161; CHECK-LE-NEXT: mfvsrwz 3, 34162; CHECK-LE-NEXT: blr163;164; CHECK-BE-LABEL: test7:165; CHECK-BE: # %bb.0: # %entry166; CHECK-BE-NEXT: li 3, 8167; CHECK-BE-NEXT: vextuwlx 3, 3, 2168; CHECK-BE-NEXT: blr169entry:170 %vecext = extractelement <4 x i32> %a, i32 2171 ret i32 %vecext172}173 174define zeroext i32 @testadd_7(<4 x i32> %a, i32 zeroext %c) {175; CHECK-LE-LABEL: testadd_7:176; CHECK-LE: # %bb.0: # %entry177; CHECK-LE-NEXT: mfvsrwz 3, 34178; CHECK-LE-NEXT: add 3, 3, 5179; CHECK-LE-NEXT: clrldi 3, 3, 32180; CHECK-LE-NEXT: blr181;182; CHECK-BE-LABEL: testadd_7:183; CHECK-BE: # %bb.0: # %entry184; CHECK-BE-NEXT: li 3, 8185; CHECK-BE-NEXT: vextuwlx 3, 3, 2186; CHECK-BE-NEXT: add 3, 3, 5187; CHECK-BE-NEXT: clrldi 3, 3, 32188; CHECK-BE-NEXT: blr189entry:190 %vecext = extractelement <4 x i32> %a, i32 2191 %add = add i32 %vecext, %c192 ret i32 %add193}194 195define signext i32 @test8(<4 x i32> %a) {196; CHECK-LE-LABEL: test8:197; CHECK-LE: # %bb.0: # %entry198; CHECK-LE-NEXT: mfvsrwz 3, 34199; CHECK-LE-NEXT: extsw 3, 3200; CHECK-LE-NEXT: blr201;202; CHECK-BE-LABEL: test8:203; CHECK-BE: # %bb.0: # %entry204; CHECK-BE-NEXT: li 3, 8205; CHECK-BE-NEXT: vextuwlx 3, 3, 2206; CHECK-BE-NEXT: extsw 3, 3207; CHECK-BE-NEXT: blr208entry:209 %vecext = extractelement <4 x i32> %a, i32 2210 ret i32 %vecext211}212 213define signext i32 @testadd_8(<4 x i32> %a, i32 signext %c) {214; CHECK-LE-LABEL: testadd_8:215; CHECK-LE: # %bb.0: # %entry216; CHECK-LE-NEXT: mfvsrwz 3, 34217; CHECK-LE-NEXT: add 3, 3, 5218; CHECK-LE-NEXT: extsw 3, 3219; CHECK-LE-NEXT: blr220;221; CHECK-BE-LABEL: testadd_8:222; CHECK-BE: # %bb.0: # %entry223; CHECK-BE-NEXT: li 3, 8224; CHECK-BE-NEXT: vextuwlx 3, 3, 2225; CHECK-BE-NEXT: add 3, 3, 5226; CHECK-BE-NEXT: extsw 3, 3227; CHECK-BE-NEXT: blr228entry:229 %vecext = extractelement <4 x i32> %a, i32 2230 %add = add nsw i32 %vecext, %c231 ret i32 %add232}233 234; When extracting word element 1 on BE, it's better to use mfvsrwz rather than vextuwlx235define signext i32 @test9(<4 x i32> %a) {236; CHECK-LE-LABEL: test9:237; CHECK-LE: # %bb.0: # %entry238; CHECK-LE-NEXT: li 3, 4239; CHECK-LE-NEXT: vextuwrx 3, 3, 2240; CHECK-LE-NEXT: extsw 3, 3241; CHECK-LE-NEXT: blr242;243; CHECK-BE-LABEL: test9:244; CHECK-BE: # %bb.0: # %entry245; CHECK-BE-NEXT: mfvsrwz 3, 34246; CHECK-BE-NEXT: extsw 3, 3247; CHECK-BE-NEXT: blr248entry:249 %vecext = extractelement <4 x i32> %a, i32 1250 ret i32 %vecext251}252 253define signext i32 @testadd_9(<4 x i32> %a, i32 signext %c) {254; CHECK-LE-LABEL: testadd_9:255; CHECK-LE: # %bb.0: # %entry256; CHECK-LE-NEXT: li 3, 4257; CHECK-LE-NEXT: vextuwrx 3, 3, 2258; CHECK-LE-NEXT: add 3, 3, 5259; CHECK-LE-NEXT: extsw 3, 3260; CHECK-LE-NEXT: blr261;262; CHECK-BE-LABEL: testadd_9:263; CHECK-BE: # %bb.0: # %entry264; CHECK-BE-NEXT: mfvsrwz 3, 34265; CHECK-BE-NEXT: add 3, 3, 5266; CHECK-BE-NEXT: extsw 3, 3267; CHECK-BE-NEXT: blr268entry:269 %vecext = extractelement <4 x i32> %a, i32 1270 %add = add nsw i32 %vecext, %c271 ret i32 %add272}273