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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-LE3; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-BE4 5define <4 x i32> @vextsb2wLE(<16 x i8> %a) {6; CHECK-LE-LABEL: vextsb2wLE:7; CHECK-LE: # %bb.0: # %entry8; CHECK-LE-NEXT: vextsb2w 2, 29; CHECK-LE-NEXT: blr10;11; CHECK-BE-LABEL: vextsb2wLE:12; CHECK-BE: # %bb.0: # %entry13; CHECK-BE-NEXT: addis 3, 2, .LCPI0_0@toc@ha14; CHECK-BE-NEXT: addi 3, 3, .LCPI0_0@toc@l15; CHECK-BE-NEXT: lxv 0, 0(3)16; CHECK-BE-NEXT: xxperm 34, 34, 017; CHECK-BE-NEXT: vextsb2w 2, 218; CHECK-BE-NEXT: blr19 20entry:21 %vecext = extractelement <16 x i8> %a, i32 022 %conv = sext i8 %vecext to i3223 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 024 %vecext1 = extractelement <16 x i8> %a, i32 425 %conv2 = sext i8 %vecext1 to i3226 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 127 %vecext4 = extractelement <16 x i8> %a, i32 828 %conv5 = sext i8 %vecext4 to i3229 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 230 %vecext7 = extractelement <16 x i8> %a, i32 1231 %conv8 = sext i8 %vecext7 to i3232 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 333 ret <4 x i32> %vecinit934}35 36define <2 x i64> @vextsb2dLE(<16 x i8> %a) {37; CHECK-LE-LABEL: vextsb2dLE:38; CHECK-LE: # %bb.0: # %entry39; CHECK-LE-NEXT: vextsb2d 2, 240; CHECK-LE-NEXT: blr41;42; CHECK-BE-LABEL: vextsb2dLE:43; CHECK-BE: # %bb.0: # %entry44; CHECK-BE-NEXT: addis 3, 2, .LCPI1_0@toc@ha45; CHECK-BE-NEXT: addi 3, 3, .LCPI1_0@toc@l46; CHECK-BE-NEXT: lxv 0, 0(3)47; CHECK-BE-NEXT: xxperm 34, 34, 048; CHECK-BE-NEXT: vextsb2d 2, 249; CHECK-BE-NEXT: blr50 51entry:52 %vecext = extractelement <16 x i8> %a, i32 053 %conv = sext i8 %vecext to i6454 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 055 %vecext1 = extractelement <16 x i8> %a, i32 856 %conv2 = sext i8 %vecext1 to i6457 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 158 ret <2 x i64> %vecinit359}60 61define <4 x i32> @vextsh2wLE(<8 x i16> %a) {62; CHECK-LE-LABEL: vextsh2wLE:63; CHECK-LE: # %bb.0: # %entry64; CHECK-LE-NEXT: vextsh2w 2, 265; CHECK-LE-NEXT: blr66;67; CHECK-BE-LABEL: vextsh2wLE:68; CHECK-BE: # %bb.0: # %entry69; CHECK-BE-NEXT: addis 3, 2, .LCPI2_0@toc@ha70; CHECK-BE-NEXT: addi 3, 3, .LCPI2_0@toc@l71; CHECK-BE-NEXT: lxv 0, 0(3)72; CHECK-BE-NEXT: xxperm 34, 34, 073; CHECK-BE-NEXT: vextsh2w 2, 274; CHECK-BE-NEXT: blr75 76entry:77 %vecext = extractelement <8 x i16> %a, i32 078 %conv = sext i16 %vecext to i3279 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 080 %vecext1 = extractelement <8 x i16> %a, i32 281 %conv2 = sext i16 %vecext1 to i3282 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 183 %vecext4 = extractelement <8 x i16> %a, i32 484 %conv5 = sext i16 %vecext4 to i3285 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 286 %vecext7 = extractelement <8 x i16> %a, i32 687 %conv8 = sext i16 %vecext7 to i3288 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 389 ret <4 x i32> %vecinit990}91 92define <2 x i64> @vextsh2dLE(<8 x i16> %a) {93; CHECK-LE-LABEL: vextsh2dLE:94; CHECK-LE: # %bb.0: # %entry95; CHECK-LE-NEXT: vextsh2d 2, 296; CHECK-LE-NEXT: blr97;98; CHECK-BE-LABEL: vextsh2dLE:99; CHECK-BE: # %bb.0: # %entry100; CHECK-BE-NEXT: addis 3, 2, .LCPI3_0@toc@ha101; CHECK-BE-NEXT: addi 3, 3, .LCPI3_0@toc@l102; CHECK-BE-NEXT: lxv 0, 0(3)103; CHECK-BE-NEXT: xxperm 34, 34, 0104; CHECK-BE-NEXT: vextsh2d 2, 2105; CHECK-BE-NEXT: blr106 107entry:108 %vecext = extractelement <8 x i16> %a, i32 0109 %conv = sext i16 %vecext to i64110 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0111 %vecext1 = extractelement <8 x i16> %a, i32 4112 %conv2 = sext i16 %vecext1 to i64113 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1114 ret <2 x i64> %vecinit3115}116 117define <2 x i64> @vextsw2dLE(<4 x i32> %a) {118; CHECK-LE-LABEL: vextsw2dLE:119; CHECK-LE: # %bb.0: # %entry120; CHECK-LE-NEXT: vextsw2d 2, 2121; CHECK-LE-NEXT: blr122;123; CHECK-BE-LABEL: vextsw2dLE:124; CHECK-BE: # %bb.0: # %entry125; CHECK-BE-NEXT: vmrgew 2, 2, 2126; CHECK-BE-NEXT: vextsw2d 2, 2127; CHECK-BE-NEXT: blr128 129entry:130 %vecext = extractelement <4 x i32> %a, i32 0131 %conv = sext i32 %vecext to i64132 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0133 %vecext1 = extractelement <4 x i32> %a, i32 2134 %conv2 = sext i32 %vecext1 to i64135 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1136 ret <2 x i64> %vecinit3137}138 139define <4 x i32> @vextsb2wBE(<16 x i8> %a) {140; CHECK-LE-LABEL: vextsb2wBE:141; CHECK-LE: # %bb.0: # %entry142; CHECK-LE-NEXT: vsldoi 2, 2, 2, 13143; CHECK-LE-NEXT: vextsb2w 2, 2144; CHECK-LE-NEXT: blr145;146; CHECK-BE-LABEL: vextsb2wBE:147; CHECK-BE: # %bb.0: # %entry148; CHECK-BE-NEXT: vextsb2w 2, 2149; CHECK-BE-NEXT: blr150entry:151 %vecext = extractelement <16 x i8> %a, i32 3152 %conv = sext i8 %vecext to i32153 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0154 %vecext1 = extractelement <16 x i8> %a, i32 7155 %conv2 = sext i8 %vecext1 to i32156 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1157 %vecext4 = extractelement <16 x i8> %a, i32 11158 %conv5 = sext i8 %vecext4 to i32159 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2160 %vecext7 = extractelement <16 x i8> %a, i32 15161 %conv8 = sext i8 %vecext7 to i32162 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3163 ret <4 x i32> %vecinit9164}165 166define <2 x i64> @vextsb2dBE(<16 x i8> %a) {167; CHECK-LE-LABEL: vextsb2dBE:168; CHECK-LE: # %bb.0: # %entry169; CHECK-LE-NEXT: vsldoi 2, 2, 2, 9170; CHECK-LE-NEXT: vextsb2d 2, 2171; CHECK-LE-NEXT: blr172;173; CHECK-BE-LABEL: vextsb2dBE:174; CHECK-BE: # %bb.0: # %entry175; CHECK-BE-NEXT: vextsb2d 2, 2176; CHECK-BE-NEXT: blr177entry:178 %vecext = extractelement <16 x i8> %a, i32 7179 %conv = sext i8 %vecext to i64180 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0181 %vecext1 = extractelement <16 x i8> %a, i32 15182 %conv2 = sext i8 %vecext1 to i64183 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1184 ret <2 x i64> %vecinit3185}186 187define <4 x i32> @vextsh2wBE(<8 x i16> %a) {188; CHECK-LE-LABEL: vextsh2wBE:189; CHECK-LE: # %bb.0: # %entry190; CHECK-LE-NEXT: vsldoi 2, 2, 2, 14191; CHECK-LE-NEXT: vextsh2w 2, 2192; CHECK-LE-NEXT: blr193;194; CHECK-BE-LABEL: vextsh2wBE:195; CHECK-BE: # %bb.0: # %entry196; CHECK-BE-NEXT: vextsh2w 2, 2197; CHECK-BE-NEXT: blr198entry:199 %vecext = extractelement <8 x i16> %a, i32 1200 %conv = sext i16 %vecext to i32201 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0202 %vecext1 = extractelement <8 x i16> %a, i32 3203 %conv2 = sext i16 %vecext1 to i32204 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1205 %vecext4 = extractelement <8 x i16> %a, i32 5206 %conv5 = sext i16 %vecext4 to i32207 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2208 %vecext7 = extractelement <8 x i16> %a, i32 7209 %conv8 = sext i16 %vecext7 to i32210 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3211 ret <4 x i32> %vecinit9212}213 214define <2 x i64> @vextsh2dBE(<8 x i16> %a) {215; CHECK-LE-LABEL: vextsh2dBE:216; CHECK-LE: # %bb.0: # %entry217; CHECK-LE-NEXT: vsldoi 2, 2, 2, 10218; CHECK-LE-NEXT: vextsh2d 2, 2219; CHECK-LE-NEXT: blr220;221; CHECK-BE-LABEL: vextsh2dBE:222; CHECK-BE: # %bb.0: # %entry223; CHECK-BE-NEXT: vextsh2d 2, 2224; CHECK-BE-NEXT: blr225entry:226 %vecext = extractelement <8 x i16> %a, i32 3227 %conv = sext i16 %vecext to i64228 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0229 %vecext1 = extractelement <8 x i16> %a, i32 7230 %conv2 = sext i16 %vecext1 to i64231 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1232 ret <2 x i64> %vecinit3233}234 235define <2 x i64> @vextsw2dBE(<4 x i32> %a) {236; CHECK-LE-LABEL: vextsw2dBE:237; CHECK-LE: # %bb.0: # %entry238; CHECK-LE-NEXT: vsldoi 2, 2, 2, 12239; CHECK-LE-NEXT: vextsw2d 2, 2240; CHECK-LE-NEXT: blr241;242; CHECK-BE-LABEL: vextsw2dBE:243; CHECK-BE: # %bb.0: # %entry244; CHECK-BE-NEXT: vextsw2d 2, 2245; CHECK-BE-NEXT: blr246entry:247 %vecext = extractelement <4 x i32> %a, i32 1248 %conv = sext i32 %vecext to i64249 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0250 %vecext1 = extractelement <4 x i32> %a, i32 3251 %conv2 = sext i32 %vecext1 to i64252 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1253 ret <2 x i64> %vecinit3254}255 256define <2 x i64> @vextDiffVectors(<4 x i32> %a, <4 x i32> %b) {257; CHECK-LE-LABEL: vextDiffVectors:258; CHECK-LE: # %bb.0: # %entry259; CHECK-LE-NEXT: li 3, 0260; CHECK-LE-NEXT: mfvsrwz 4, 35261; CHECK-LE-NEXT: vextuwrx 3, 3, 2262; CHECK-LE-NEXT: extsw 4, 4263; CHECK-LE-NEXT: extsw 3, 3264; CHECK-LE-NEXT: mtvsrdd 34, 4, 3265; CHECK-LE-NEXT: blr266;267; CHECK-BE-LABEL: vextDiffVectors:268; CHECK-BE: # %bb.0: # %entry269; CHECK-BE-NEXT: li 3, 0270; CHECK-BE-NEXT: li 4, 8271; CHECK-BE-NEXT: vextuwlx 3, 3, 2272; CHECK-BE-NEXT: vextuwlx 4, 4, 3273; CHECK-BE-NEXT: extsw 3, 3274; CHECK-BE-NEXT: extsw 4, 4275; CHECK-BE-NEXT: mtvsrdd 34, 3, 4276; CHECK-BE-NEXT: blr277 278entry:279 %vecext = extractelement <4 x i32> %a, i32 0280 %conv = sext i32 %vecext to i64281 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0282 %vecext1 = extractelement <4 x i32> %b, i32 2283 %conv2 = sext i32 %vecext1 to i64284 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1285 ret <2 x i64> %vecinit3286}287 288define <8 x i16> @testInvalidExtend(<16 x i8> %a) {289; CHECK-LE-LABEL: testInvalidExtend:290; CHECK-LE: # %bb.0: # %entry291; CHECK-LE-NEXT: li 3, 0292; CHECK-LE-NEXT: li 4, 2293; CHECK-LE-NEXT: li 5, 4294; CHECK-LE-NEXT: li 6, 6295; CHECK-LE-NEXT: vextubrx 3, 3, 2296; CHECK-LE-NEXT: vextubrx 4, 4, 2297; CHECK-LE-NEXT: vextubrx 5, 5, 2298; CHECK-LE-NEXT: vextubrx 6, 6, 2299; CHECK-LE-NEXT: li 7, 8300; CHECK-LE-NEXT: li 8, 10301; CHECK-LE-NEXT: li 9, 12302; CHECK-LE-NEXT: li 10, 14303; CHECK-LE-NEXT: extsb 3, 3304; CHECK-LE-NEXT: extsb 4, 4305; CHECK-LE-NEXT: extsb 5, 5306; CHECK-LE-NEXT: extsb 6, 6307; CHECK-LE-NEXT: vextubrx 7, 7, 2308; CHECK-LE-NEXT: vextubrx 8, 8, 2309; CHECK-LE-NEXT: extsb 7, 7310; CHECK-LE-NEXT: extsb 8, 8311; CHECK-LE-NEXT: mtvsrd 35, 4312; CHECK-LE-NEXT: vextubrx 9, 9, 2313; CHECK-LE-NEXT: vextubrx 10, 10, 2314; CHECK-LE-NEXT: mtvsrd 34, 3315; CHECK-LE-NEXT: mtvsrd 36, 6316; CHECK-LE-NEXT: extsb 9, 9317; CHECK-LE-NEXT: extsb 10, 10318; CHECK-LE-NEXT: vmrghh 2, 3, 2319; CHECK-LE-NEXT: mtvsrd 35, 5320; CHECK-LE-NEXT: vmrghh 3, 4, 3321; CHECK-LE-NEXT: mtvsrd 36, 10322; CHECK-LE-NEXT: xxmrglw 0, 35, 34323; CHECK-LE-NEXT: mtvsrd 34, 7324; CHECK-LE-NEXT: mtvsrd 35, 8325; CHECK-LE-NEXT: vmrghh 2, 3, 2326; CHECK-LE-NEXT: mtvsrd 35, 9327; CHECK-LE-NEXT: vmrghh 3, 4, 3328; CHECK-LE-NEXT: xxmrglw 1, 35, 34329; CHECK-LE-NEXT: xxmrgld 34, 1, 0330; CHECK-LE-NEXT: blr331;332; CHECK-BE-LABEL: testInvalidExtend:333; CHECK-BE: # %bb.0: # %entry334; CHECK-BE-NEXT: li 9, 12335; CHECK-BE-NEXT: li 10, 14336; CHECK-BE-NEXT: li 7, 8337; CHECK-BE-NEXT: li 8, 10338; CHECK-BE-NEXT: vextublx 9, 9, 2339; CHECK-BE-NEXT: vextublx 10, 10, 2340; CHECK-BE-NEXT: vextublx 7, 7, 2341; CHECK-BE-NEXT: vextublx 8, 8, 2342; CHECK-BE-NEXT: li 5, 4343; CHECK-BE-NEXT: li 6, 6344; CHECK-BE-NEXT: li 3, 0345; CHECK-BE-NEXT: li 4, 2346; CHECK-BE-NEXT: extsb 9, 9347; CHECK-BE-NEXT: extsb 10, 10348; CHECK-BE-NEXT: extsb 7, 7349; CHECK-BE-NEXT: extsb 8, 8350; CHECK-BE-NEXT: vextublx 5, 5, 2351; CHECK-BE-NEXT: vextublx 6, 6, 2352; CHECK-BE-NEXT: extsb 5, 5353; CHECK-BE-NEXT: extsb 6, 6354; CHECK-BE-NEXT: mtfprwz 1, 9355; CHECK-BE-NEXT: addis 9, 2, .LCPI11_0@toc@ha356; CHECK-BE-NEXT: mtfprwz 0, 10357; CHECK-BE-NEXT: mtfprwz 3, 7358; CHECK-BE-NEXT: vextublx 3, 3, 2359; CHECK-BE-NEXT: extsb 3, 3360; CHECK-BE-NEXT: mtfprwz 4, 3361; CHECK-BE-NEXT: addi 9, 9, .LCPI11_0@toc@l362; CHECK-BE-NEXT: vextublx 4, 4, 2363; CHECK-BE-NEXT: extsb 4, 4364; CHECK-BE-NEXT: lxv 2, 0(9)365; CHECK-BE-NEXT: xxperm 0, 1, 2366; CHECK-BE-NEXT: mtfprwz 1, 8367; CHECK-BE-NEXT: xxperm 1, 3, 2368; CHECK-BE-NEXT: mtfprwz 3, 5369; CHECK-BE-NEXT: xxmrghw 0, 1, 0370; CHECK-BE-NEXT: mtfprwz 1, 6371; CHECK-BE-NEXT: xxperm 1, 3, 2372; CHECK-BE-NEXT: mtfprwz 3, 4373; CHECK-BE-NEXT: xxperm 3, 4, 2374; CHECK-BE-NEXT: xxmrghw 1, 3, 1375; CHECK-BE-NEXT: xxmrghd 34, 1, 0376; CHECK-BE-NEXT: blr377entry:378 379 380 %vecext = extractelement <16 x i8> %a, i32 0381 %conv = sext i8 %vecext to i16382 %vecinit = insertelement <8 x i16> undef, i16 %conv, i32 0383 %vecext1 = extractelement <16 x i8> %a, i32 2384 %conv2 = sext i8 %vecext1 to i16385 %vecinit3 = insertelement <8 x i16> %vecinit, i16 %conv2, i32 1386 %vecext4 = extractelement <16 x i8> %a, i32 4387 %conv5 = sext i8 %vecext4 to i16388 %vecinit6 = insertelement <8 x i16> %vecinit3, i16 %conv5, i32 2389 %vecext7 = extractelement <16 x i8> %a, i32 6390 %conv8 = sext i8 %vecext7 to i16391 %vecinit9 = insertelement <8 x i16> %vecinit6, i16 %conv8, i32 3392 %vecext10 = extractelement <16 x i8> %a, i32 8393 %conv11 = sext i8 %vecext10 to i16394 %vecinit12 = insertelement <8 x i16> %vecinit9, i16 %conv11, i32 4395 %vecext13 = extractelement <16 x i8> %a, i32 10396 %conv14 = sext i8 %vecext13 to i16397 %vecinit15 = insertelement <8 x i16> %vecinit12, i16 %conv14, i32 5398 %vecext16 = extractelement <16 x i8> %a, i32 12399 %conv17 = sext i8 %vecext16 to i16400 %vecinit18 = insertelement <8 x i16> %vecinit15, i16 %conv17, i32 6401 %vecext19 = extractelement <16 x i8> %a, i32 14402 %conv20 = sext i8 %vecext19 to i16403 %vecinit21 = insertelement <8 x i16> %vecinit18, i16 %conv20, i32 7404 ret <8 x i16> %vecinit21405}406