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1; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -mattr=-power8-altivec | FileCheck %s2; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -mcpu=pwr7 | FileCheck %s3; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -mcpu=pwr8 -mattr=-power8-altivec | FileCheck %s -check-prefix=CHECK-LE4; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -mattr=+vsx -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-VSX5; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec -mattr=+vsx -mcpu=pwr8 -mattr=-power8-altivec | FileCheck %s -check-prefix=CHECK-LE-VSX6 7define <4 x i32> @test_v4i32(ptr %X, ptr %Y) {8 %tmp = load <4 x i32>, ptr %X ; <<4 x i32>> [#uses=1]9 %tmp2 = load <4 x i32>, ptr %Y ; <<4 x i32>> [#uses=1]10 %tmp3 = mul <4 x i32> %tmp, %tmp2 ; <<4 x i32>> [#uses=1]11 ret <4 x i32> %tmp312}13; CHECK-LABEL: test_v4i32:14; CHECK: vmsumuhm15; CHECK-NOT: mullw16; CHECK-LE-LABEL: test_v4i32:17; CHECK-LE: vmsumuhm18; CHECK-LE-NOT: mullw19; CHECK-VSX-LABEL: test_v4i32:20; CHECK-VSX: vmsumuhm21; CHECK-VSX-NOT: mullw22; CHECK-LE-VSX-LABEL: test_v4i32:23; CHECK-LE-VSX: vmsumuhm24; CHECK-LE-VSX-NOT: mullw25 26define <8 x i16> @test_v8i16(ptr %X, ptr %Y) {27 %tmp = load <8 x i16>, ptr %X ; <<8 x i16>> [#uses=1]28 %tmp2 = load <8 x i16>, ptr %Y ; <<8 x i16>> [#uses=1]29 %tmp3 = mul <8 x i16> %tmp, %tmp2 ; <<8 x i16>> [#uses=1]30 ret <8 x i16> %tmp331}32; CHECK-LABEL: test_v8i16:33; CHECK: vmladduhm34; CHECK-NOT: mullw35; CHECK-LE-LABEL: test_v8i16:36; CHECK-LE: vmladduhm37; CHECK-LE-NOT: mullw38; CHECK-VSX-LABEL: test_v8i16:39; CHECK-VSX: vmladduhm40; CHECK-VSX-NOT: mullw41; CHECK-LE-VSX-LABEL: test_v8i16:42; CHECK-LE-VSX: vmladduhm43; CHECK-LE-VSX-NOT: mullw44 45define <16 x i8> @test_v16i8(ptr %X, ptr %Y) {46 %tmp = load <16 x i8>, ptr %X ; <<16 x i8>> [#uses=1]47 %tmp2 = load <16 x i8>, ptr %Y ; <<16 x i8>> [#uses=1]48 %tmp3 = mul <16 x i8> %tmp, %tmp2 ; <<16 x i8>> [#uses=1]49 ret <16 x i8> %tmp350}51; CHECK-LABEL: test_v16i8:52; CHECK: vmuloub53; CHECK: vmuleub54; CHECK-NOT: mullw55; CHECK-LE-LABEL: test_v16i8:56; CHECK-LE: vmuloub [[REG1:[0-9]+]]57; CHECK-LE: vmuleub [[REG2:[0-9]+]]58; CHECK-LE: vperm {{[0-9]+}}, [[REG2]], [[REG1]]59; CHECK-LE-NOT: mullw60; CHECK-VSX-LABEL: test_v16i8:61; CHECK-VSX: vmuloub62; CHECK-VSX: vmuleub63; CHECK-VSX-NOT: mullw64; CHECK-LE-VSX-LABEL: test_v16i8:65; CHECK-LE-VSX: vmuloub [[REG1:[0-9]+]]66; CHECK-LE-VSX: vmuleub [[REG2:[0-9]+]]67; CHECK-LE-VSX: vperm {{[0-9]+}}, [[REG2]], [[REG1]]68; CHECK-LE-VSX-NOT: mullw69 70define <4 x float> @test_float(ptr %X, ptr %Y) {71 %tmp = load <4 x float>, ptr %X72 %tmp2 = load <4 x float>, ptr %Y73 %tmp3 = fmul <4 x float> %tmp, %tmp274 ret <4 x float> %tmp375}76; Check the creation of a negative zero float vector by creating a vector of77; all bits set and shifting it 31 bits to left, resulting a an vector of 78; 4 x 0x80000000 (-0.0 as float).79; CHECK-LABEL: test_float:80; CHECK: vspltisw [[ZNEG:[0-9]+]], -181; CHECK: vslw {{[0-9]+}}, [[ZNEG]], [[ZNEG]]82; CHECK: vmaddfp83; CHECK-LE-LABEL: test_float:84; CHECK-LE: vspltisw [[ZNEG:[0-9]+]], -185; CHECK-LE: vslw {{[0-9]+}}, [[ZNEG]], [[ZNEG]]86; CHECK-LE: vmaddfp87; CHECK-VSX-LABEL: test_float:88; CHECK-VSX: xvmulsp89; CHECK-LE-VSX-LABEL: test_float:90; CHECK-LE-VSX: xvmulsp91