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1; Test the vector rotate and shift doubleword instructions that were added in P82; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s3; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s4 5declare <2 x i64> @llvm.ppc.altivec.vrld(<2 x i64>, <2 x i64>) nounwind readnone6declare <2 x i64> @llvm.ppc.altivec.vsld(<2 x i64>, <2 x i64>) nounwind readnone7declare <2 x i64> @llvm.ppc.altivec.vsrd(<2 x i64>, <2 x i64>) nounwind readnone8declare <2 x i64> @llvm.ppc.altivec.vsrad(<2 x i64>, <2 x i64>) nounwind readnone9 10define <2 x i64> @test_vrld(<2 x i64> %x, <2 x i64> %y) nounwind readnone {11 %tmp = tail call <2 x i64> @llvm.ppc.altivec.vrld(<2 x i64> %x, <2 x i64> %y)12 ret <2 x i64> %tmp13; CHECK: vrld 2, 2, 314}15 16define <2 x i64> @test_vsld(<2 x i64> %x, <2 x i64> %y) nounwind readnone {17 %tmp = shl <2 x i64> %x, %y18 ret <2 x i64> %tmp19; CHECK-LABEL: @test_vsld20; CHECK: vsld 2, 2, 321}22 23define <2 x i64> @test_vsrd(<2 x i64> %x, <2 x i64> %y) nounwind readnone {24 %tmp = lshr <2 x i64> %x, %y25 ret <2 x i64> %tmp26; CHECK-LABEL: @test_vsrd27; CHECK: vsrd 2, 2, 328}29 30define <2 x i64> @test_vsrad(<2 x i64> %x, <2 x i64> %y) nounwind readnone {31 %tmp = ashr <2 x i64> %x, %y32 ret <2 x i64> %tmp33; CHECK-LABEL: @test_vsrad34; CHECK: vsrad 2, 2, 335}36 37