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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -mcpu=pwr7 | FileCheck %s3 4define void @VPKUHUM_xy(ptr %A, ptr %B) {5; CHECK-LABEL: VPKUHUM_xy:6; CHECK: # %bb.0: # %entry7; CHECK-NEXT: lvx 2, 0, 38; CHECK-NEXT: lvx 3, 0, 49; CHECK-NEXT: vpkuhum 2, 3, 210; CHECK-NEXT: stvx 2, 0, 311; CHECK-NEXT: blr12entry:13 %tmp = load <16 x i8>, ptr %A14 %tmp2 = load <16 x i8>, ptr %B15 %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>16 store <16 x i8> %tmp3, ptr %A17 ret void18}19 20define void @VPKUHUM_xx(ptr %A) {21; CHECK-LABEL: VPKUHUM_xx:22; CHECK: # %bb.0: # %entry23; CHECK-NEXT: lvx 2, 0, 324; CHECK-NEXT: vpkuhum 2, 2, 225; CHECK-NEXT: stvx 2, 0, 326; CHECK-NEXT: blr27entry:28 %tmp = load <16 x i8>, ptr %A29 %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>30 store <16 x i8> %tmp2, ptr %A31 ret void32}33 34define void @VPKUWUM_xy(ptr %A, ptr %B) {35; CHECK-LABEL: VPKUWUM_xy:36; CHECK: # %bb.0: # %entry37; CHECK-NEXT: lvx 2, 0, 338; CHECK-NEXT: lvx 3, 0, 439; CHECK-NEXT: vpkuwum 2, 3, 240; CHECK-NEXT: stvx 2, 0, 341; CHECK-NEXT: blr42entry:43 %tmp = load <16 x i8>, ptr %A44 %tmp2 = load <16 x i8>, ptr %B45 %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13, i32 16, i32 17, i32 20, i32 21, i32 24, i32 25, i32 28, i32 29>46 store <16 x i8> %tmp3, ptr %A47 ret void48}49 50define void @VPKUWUM_xx(ptr %A) {51; CHECK-LABEL: VPKUWUM_xx:52; CHECK: # %bb.0: # %entry53; CHECK-NEXT: lvx 2, 0, 354; CHECK-NEXT: vpkuwum 2, 2, 255; CHECK-NEXT: stvx 2, 0, 356; CHECK-NEXT: blr57entry:58 %tmp = load <16 x i8>, ptr %A59 %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13, i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13>60 store <16 x i8> %tmp2, ptr %A61 ret void62}63 64define void @VMRGLB_xy(ptr %A, ptr %B) {65; CHECK-LABEL: VMRGLB_xy:66; CHECK: # %bb.0: # %entry67; CHECK-NEXT: lvx 2, 0, 368; CHECK-NEXT: lvx 3, 0, 469; CHECK-NEXT: vmrglb 2, 3, 270; CHECK-NEXT: stvx 2, 0, 371; CHECK-NEXT: blr72entry:73 %tmp = load <16 x i8>, ptr %A74 %tmp2 = load <16 x i8>, ptr %B75 %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>76 store <16 x i8> %tmp3, ptr %A77 ret void78}79 80define void @VMRGLB_xx(ptr %A) {81; CHECK-LABEL: VMRGLB_xx:82; CHECK: # %bb.0: # %entry83; CHECK-NEXT: lvx 2, 0, 384; CHECK-NEXT: vmrglb 2, 2, 285; CHECK-NEXT: stvx 2, 0, 386; CHECK-NEXT: blr87entry:88 %tmp = load <16 x i8>, ptr %A89 %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 3, i32 3, i32 4, i32 4, i32 5, i32 5, i32 6, i32 6, i32 7, i32 7>90 store <16 x i8> %tmp2, ptr %A91 ret void92}93 94define void @VMRGHB_xy(ptr %A, ptr %B) {95; CHECK-LABEL: VMRGHB_xy:96; CHECK: # %bb.0: # %entry97; CHECK-NEXT: lvx 2, 0, 398; CHECK-NEXT: lvx 3, 0, 499; CHECK-NEXT: vmrghb 2, 3, 2100; CHECK-NEXT: stvx 2, 0, 3101; CHECK-NEXT: blr102entry:103 %tmp = load <16 x i8>, ptr %A104 %tmp2 = load <16 x i8>, ptr %B105 %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>106 store <16 x i8> %tmp3, ptr %A107 ret void108}109 110define void @VMRGHB_xx(ptr %A) {111; CHECK-LABEL: VMRGHB_xx:112; CHECK: # %bb.0: # %entry113; CHECK-NEXT: lvx 2, 0, 3114; CHECK-NEXT: vmrghb 2, 2, 2115; CHECK-NEXT: stvx 2, 0, 3116; CHECK-NEXT: blr117entry:118 %tmp = load <16 x i8>, ptr %A119 %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 8, i32 8, i32 9, i32 9, i32 10, i32 10, i32 11, i32 11, i32 12, i32 12, i32 13, i32 13, i32 14, i32 14, i32 15, i32 15>120 store <16 x i8> %tmp2, ptr %A121 ret void122}123 124define void @VMRGLH_xy(ptr %A, ptr %B) {125; CHECK-LABEL: VMRGLH_xy:126; CHECK: # %bb.0: # %entry127; CHECK-NEXT: lvx 2, 0, 3128; CHECK-NEXT: lvx 3, 0, 4129; CHECK-NEXT: vmrglh 2, 3, 2130; CHECK-NEXT: stvx 2, 0, 3131; CHECK-NEXT: blr132entry:133 %tmp = load <16 x i8>, ptr %A134 %tmp2 = load <16 x i8>, ptr %B135 %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 16, i32 17, i32 2, i32 3, i32 18, i32 19, i32 4, i32 5, i32 20, i32 21, i32 6, i32 7, i32 22, i32 23>136 store <16 x i8> %tmp3, ptr %A137 ret void138}139 140define void @VMRGLH_xx(ptr %A) {141; CHECK-LABEL: VMRGLH_xx:142; CHECK: # %bb.0: # %entry143; CHECK-NEXT: lvx 2, 0, 3144; CHECK-NEXT: vmrglh 2, 2, 2145; CHECK-NEXT: stvx 2, 0, 3146; CHECK-NEXT: blr147entry:148 %tmp = load <16 x i8>, ptr %A149 %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 1, i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 4, i32 5, i32 4, i32 5, i32 6, i32 7, i32 6, i32 7>150 store <16 x i8> %tmp2, ptr %A151 ret void152}153 154define void @VMRGHH_xy(ptr %A, ptr %B) {155; CHECK-LABEL: VMRGHH_xy:156; CHECK: # %bb.0: # %entry157; CHECK-NEXT: lvx 2, 0, 3158; CHECK-NEXT: lvx 3, 0, 4159; CHECK-NEXT: vmrghh 2, 3, 2160; CHECK-NEXT: stvx 2, 0, 3161; CHECK-NEXT: blr162entry:163 %tmp = load <16 x i8>, ptr %A164 %tmp2 = load <16 x i8>, ptr %B165 %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 9, i32 24, i32 25, i32 10, i32 11, i32 26, i32 27, i32 12, i32 13, i32 28, i32 29, i32 14, i32 15, i32 30, i32 31>166 store <16 x i8> %tmp3, ptr %A167 ret void168}169 170define void @VMRGHH_xx(ptr %A) {171; CHECK-LABEL: VMRGHH_xx:172; CHECK: # %bb.0: # %entry173; CHECK-NEXT: lvx 2, 0, 3174; CHECK-NEXT: vmrghh 2, 2, 2175; CHECK-NEXT: stvx 2, 0, 3176; CHECK-NEXT: blr177entry:178 %tmp = load <16 x i8>, ptr %A179 %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 8, i32 9, i32 8, i32 9, i32 10, i32 11, i32 10, i32 11, i32 12, i32 13, i32 12, i32 13, i32 14, i32 15, i32 14, i32 15>180 store <16 x i8> %tmp2, ptr %A181 ret void182}183 184define void @VMRGLW_xy(ptr %A, ptr %B) {185; CHECK-LABEL: VMRGLW_xy:186; CHECK: # %bb.0: # %entry187; CHECK-NEXT: lvx 2, 0, 3188; CHECK-NEXT: lvx 3, 0, 4189; CHECK-NEXT: vmrglw 2, 3, 2190; CHECK-NEXT: stvx 2, 0, 3191; CHECK-NEXT: blr192entry:193 %tmp = load <16 x i8>, ptr %A194 %tmp2 = load <16 x i8>, ptr %B195 %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 17, i32 18, i32 19, i32 4, i32 5, i32 6, i32 7, i32 20, i32 21, i32 22, i32 23>196 store <16 x i8> %tmp3, ptr %A197 ret void198}199 200define void @VMRGLW_xx(ptr %A) {201; CHECK-LABEL: VMRGLW_xx:202; CHECK: # %bb.0: # %entry203; CHECK-NEXT: lvx 2, 0, 3204; CHECK-NEXT: vmrglw 2, 2, 2205; CHECK-NEXT: stvx 2, 0, 3206; CHECK-NEXT: blr207entry:208 %tmp = load <16 x i8>, ptr %A209 %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>210 store <16 x i8> %tmp2, ptr %A211 ret void212}213 214define void @VMRGHW_xy(ptr %A, ptr %B) {215; CHECK-LABEL: VMRGHW_xy:216; CHECK: # %bb.0: # %entry217; CHECK-NEXT: lvx 2, 0, 3218; CHECK-NEXT: lvx 3, 0, 4219; CHECK-NEXT: vmrghw 2, 3, 2220; CHECK-NEXT: stvx 2, 0, 3221; CHECK-NEXT: blr222entry:223 %tmp = load <16 x i8>, ptr %A224 %tmp2 = load <16 x i8>, ptr %B225 %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 24, i32 25, i32 26, i32 27, i32 12, i32 13, i32 14, i32 15, i32 28, i32 29, i32 30, i32 31>226 store <16 x i8> %tmp3, ptr %A227 ret void228}229 230define void @VMRGHW_xx(ptr %A) {231; CHECK-LABEL: VMRGHW_xx:232; CHECK: # %bb.0: # %entry233; CHECK-NEXT: lvx 2, 0, 3234; CHECK-NEXT: vmrghw 2, 2, 2235; CHECK-NEXT: stvx 2, 0, 3236; CHECK-NEXT: blr237entry:238 %tmp = load <16 x i8>, ptr %A239 %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15>240 store <16 x i8> %tmp2, ptr %A241 ret void242}243 244define void @VSLDOI_xy(ptr %A, ptr %B) {245; CHECK-LABEL: VSLDOI_xy:246; CHECK: # %bb.0: # %entry247; CHECK-NEXT: lvx 2, 0, 3248; CHECK-NEXT: lvx 3, 0, 4249; CHECK-NEXT: vsldoi 2, 3, 2, 4250; CHECK-NEXT: stvx 2, 0, 3251; CHECK-NEXT: blr252entry:253 %tmp = load <16 x i8>, ptr %A254 %tmp2 = load <16 x i8>, ptr %B255 %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27>256 store <16 x i8> %tmp3, ptr %A257 ret void258}259 260define void @VSLDOI_xx(ptr %A) {261; CHECK-LABEL: VSLDOI_xx:262; CHECK: # %bb.0: # %entry263; CHECK-NEXT: lvx 2, 0, 3264; CHECK-NEXT: vsldoi 2, 2, 2, 4265; CHECK-NEXT: stvx 2, 0, 3266; CHECK-NEXT: blr267entry:268 %tmp = load <16 x i8>, ptr %A269 %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>270 store <16 x i8> %tmp2, ptr %A271 ret void272}273 274