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1; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | \2; RUN: FileCheck %s -check-prefix=CHECK-LE3; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | \4; RUN: FileCheck %s -check-prefix=CHECK-BE5 6; Possible LE ShuffleVector masks (Case 1):7; ShuffleVector((vector int)a, vector(int)b, 0, 1, 2, 3)8; ShuffleVector((vector int)a, vector(int)b, 7, 0, 1, 2)9; ShuffleVector((vector int)a, vector(int)b, 6, 7, 0, 1)10; ShuffleVector((vector int)a, vector(int)b, 5, 6, 7, 0)11; which targets at:12; xxsldwi a, b, 013; xxsldwi a, b, 114; xxsldwi a, b, 215; xxsldwi a, b, 316; Possible LE Swap ShuffleVector masks (Case 2):17; ShuffleVector((vector int)a, vector(int)b, 4, 5, 6, 7)18; ShuffleVector((vector int)a, vector(int)b, 3, 4, 5, 6)19; ShuffleVector((vector int)a, vector(int)b, 2, 3, 4, 5)20; ShuffleVector((vector int)a, vector(int)b, 1, 2, 3, 4)21; which targets at:22; xxsldwi b, a, 023; xxsldwi b, a, 124; xxsldwi b, a, 225; xxsldwi b, a, 326; Possible LE ShuffleVector masks when a == b, b is undef (Case 3):27; ShuffleVector((vector int)a, vector(int)a, 0, 1, 2, 3)28; ShuffleVector((vector int)a, vector(int)a, 3, 0, 1, 2)29; ShuffleVector((vector int)a, vector(int)a, 2, 3, 0, 1)30; ShuffleVector((vector int)a, vector(int)a, 1, 2, 3, 0)31; which targets at:32; xxsldwi a, a, 033; xxsldwi a, a, 134; xxsldwi a, a, 235; xxsldwi a, a, 336 37; Possible BE ShuffleVector masks (Case 4):38; ShuffleVector((vector int)a, vector(int)b, 0, 1, 2, 3)39; ShuffleVector((vector int)a, vector(int)b, 1, 2, 3, 4)40; ShuffleVector((vector int)a, vector(int)b, 2, 3, 4, 5)41; ShuffleVector((vector int)a, vector(int)b, 3, 4, 5, 6)42; which targets at:43; xxsldwi b, a, 044; xxsldwi b, a, 145; xxsldwi a, a, 246; xxsldwi a, a, 347; Possible BE Swap ShuffleVector masks (Case 5):48; ShuffleVector((vector int)a, vector(int)b, 4, 5, 6, 7)49; ShuffleVector((vector int)a, vector(int)b, 5, 6, 7, 0)50; ShuffleVector((vector int)a, vector(int)b, 6, 7, 0, 1)51; ShuffleVector((vector int)a, vector(int)b, 7, 0, 1, 2)52; which targets at:53; xxsldwi b, a, 054; xxsldwi b, a, 155; xxsldwi b, a, 256; xxsldwi b, a, 357; Possible BE ShuffleVector masks when a == b, b is undef (Case 6):58; ShuffleVector((vector int)a, vector(int)b, 0, 1, 2, 3)59; ShuffleVector((vector int)a, vector(int)a, 1, 2, 3, 0)60; ShuffleVector((vector int)a, vector(int)a, 2, 3, 0, 1)61; ShuffleVector((vector int)a, vector(int)a, 3, 0, 1, 2)62; which targets at:63; xxsldwi a, a, 064; xxsldwi a, a, 165; xxsldwi a, a, 266; xxsldwi a, a, 367 68define <4 x i32> @check_le_vec_sldwi_va_vb_0(<4 x i32> %VA, <4 x i32> %VB) {69entry:70 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 0, i32 1, i32 2, i32 3>71 ret <4 x i32> %072; CHECK-LE-LABEL: @check_le_vec_sldwi_va_vb_073; CHECK-LE: blr74}75 76define <4 x i32> @check_le_vec_sldwi_va_vb_1(<4 x i32> %VA, <4 x i32> %VB) {77entry:78 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 7, i32 0, i32 1, i32 2>79 ret <4 x i32> %080; CHECK-LE-LABEL: @check_le_vec_sldwi_va_vb_181; CHECK-LE: xxsldwi 34, 34, 35, 182; CHECK-LE: blr83}84 85define <4 x i32> @check_le_vec_sldwi_va_vb_2(<4 x i32> %VA, <4 x i32> %VB) {86entry:87 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 6, i32 7, i32 0, i32 1>88 ret <4 x i32> %089; CHECK-LE-LABEL: @check_le_vec_sldwi_va_vb_290; CHECK-LE: xxsldwi 34, 34, 35, 291; CHECK-LE: blr92}93 94define <4 x i32> @check_le_vec_sldwi_va_vb_3(<4 x i32> %VA, <4 x i32> %VB) {95entry:96 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 5, i32 6, i32 7, i32 0>97 ret <4 x i32> %098; CHECK-LE-LABEL: @check_le_vec_sldwi_va_vb_399; CHECK-LE: xxsldwi 34, 34, 35, 3100; CHECK-LE: blr101}102 103define <4 x i32> @check_le_swap_vec_sldwi_va_vb_0(<4 x i32> %VA, <4 x i32> %VB) {104entry:105 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 4, i32 5, i32 6, i32 7>106 ret <4 x i32> %0107; CHECK-LE-LABEL: @check_le_swap_vec_sldwi_va_vb_0108; CHECK-LE: vmr 2, 3109; CHECK-LE: blr110}111 112define <4 x i32> @check_le_swap_vec_sldwi_va_vb_1(<4 x i32> %VA, <4 x i32> %VB) {113entry:114 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 3, i32 4, i32 5, i32 6>115 ret <4 x i32> %0116; CHECK-LE-LABEL: @check_le_swap_vec_sldwi_va_vb_1117; CHECK-LE: xxsldwi 34, 35, 34, 1118; CHECK-LE: blr119}120 121define <4 x i32> @check_le_swap_vec_sldwi_va_vb_2(<4 x i32> %VA, <4 x i32> %VB) {122entry:123 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 2, i32 3, i32 4, i32 5>124 ret <4 x i32> %0125; CHECK-LE-LABEL: @check_le_swap_vec_sldwi_va_vb_2126; CHECK-LE: xxsldwi 34, 35, 34, 2127; CHECK-LE: blr128}129 130define <4 x i32> @check_le_swap_vec_sldwi_va_vb_3(<4 x i32> %VA, <4 x i32> %VB) {131entry:132 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 1, i32 2, i32 3, i32 4>133 ret <4 x i32> %0134; CHECK-LE-LABEL: @check_le_swap_vec_sldwi_va_vb_3135; CHECK-LE: xxsldwi 34, 35, 34, 3136; CHECK-LE: blr137}138 139define <4 x i32> @check_le_vec_sldwi_va_undef_0(<4 x i32> %VA) {140entry:141 %0 = shufflevector <4 x i32> %VA, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>142 ret <4 x i32> %0143; CHECK-LE-LABEL: @check_le_vec_sldwi_va_undef_0144; CHECK-LE: blr145}146 147define <4 x i32> @check_le_vec_sldwi_va_undef_1(<4 x i32> %VA) {148entry:149 %0 = shufflevector <4 x i32> %VA, <4 x i32> undef, <4 x i32> <i32 3, i32 0, i32 1, i32 2>150 ret <4 x i32> %0151; CHECK-BE-LABEL: @check_le_vec_sldwi_va_undef_1152; CHECK-LE: xxsldwi 34, 34, 34, 1153; CHECK-LE: blr154}155 156define <4 x i32> @check_le_vec_sldwi_va_undef_2(<4 x i32> %VA) {157entry:158 %0 = shufflevector <4 x i32> %VA, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 0, i32 1>159 ret <4 x i32> %0160; CHECK-LE-LABEL: @check_le_vec_sldwi_va_undef_2161; CHECK-LE: xxswapd 34, 34162; CHECK-LE: blr163}164 165define <4 x i32> @check_le_vec_sldwi_va_undef_3(<4 x i32> %VA) {166entry:167 %0 = shufflevector <4 x i32> %VA, <4 x i32> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0>168 ret <4 x i32> %0169; CHECK-LE-LABEL: @check_le_vec_sldwi_va_undef_3170; CHECK-LE: xxsldwi 34, 34, 34, 3171; CHECK-LE: blr172}173 174define <4 x i32> @check_be_vec_sldwi_va_vb_0(<4 x i32> %VA, <4 x i32> %VB) {175entry:176 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 0, i32 1, i32 2, i32 3>177 ret <4 x i32> %0178; CHECK-BE-LABEL: @check_be_vec_sldwi_va_vb_0179; CHECK-BE: blr180}181 182define <4 x i32> @check_be_vec_sldwi_va_vb_1(<4 x i32> %VA, <4 x i32> %VB) {183entry:184 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 1, i32 2, i32 3, i32 4>185 ret <4 x i32> %0186; CHECK-BE-LABEL: @check_be_vec_sldwi_va_vb_1187; CHECK-BE: xxsldwi 34, 34, 35, 1188; CHECK-BE: blr189}190 191define <4 x i32> @check_be_vec_sldwi_va_vb_2(<4 x i32> %VA, <4 x i32> %VB) {192entry:193 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 2, i32 3, i32 4, i32 5>194 ret <4 x i32> %0195; CHECK-BE-LABEL: @check_be_vec_sldwi_va_vb_2196; CHECK-BE: xxsldwi 34, 34, 35, 2197; CHECK-BE: blr198}199 200define <4 x i32> @check_be_vec_sldwi_va_vb_3(<4 x i32> %VA, <4 x i32> %VB) {201entry:202 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 3, i32 4, i32 5, i32 6>203 ret <4 x i32> %0204; CHECK-BE-LABEL: @check_be_vec_sldwi_va_vb_3205; CHECK-BE: xxsldwi 34, 34, 35, 3206; CHECK-BE: blr207}208 209define <4 x i32> @check_be_swap_vec_sldwi_va_vb_0(<4 x i32> %VA, <4 x i32> %VB) {210entry:211 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 4, i32 5, i32 6, i32 7>212 ret <4 x i32> %0213; CHECK-BE-LABEL: @check_be_swap_vec_sldwi_va_vb_0214; CHECK-LE: vmr 2, 3215; CHECK-BE: blr216}217 218define <4 x i32> @check_be_swap_vec_sldwi_va_vb_1(<4 x i32> %VA, <4 x i32> %VB) {219entry:220 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 5, i32 6, i32 7, i32 0>221 ret <4 x i32> %0222; CHECK-BE-LABEL: @check_be_swap_vec_sldwi_va_vb_1223; CHECK-BE: xxsldwi 34, 35, 34, 1224; CHECK-BE: blr225}226 227define <4 x i32> @check_be_swap_vec_sldwi_va_vb_2(<4 x i32> %VA, <4 x i32> %VB) {228entry:229 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 6, i32 7, i32 0, i32 1>230 ret <4 x i32> %0231; CHECK-BE-LABEL: @check_be_swap_vec_sldwi_va_vb_2232; CHECK-BE: xxsldwi 34, 35, 34, 2233; CHECK-BE: blr234}235 236define <4 x i32> @check_be_swap_vec_sldwi_va_vb_3(<4 x i32> %VA, <4 x i32> %VB) {237entry:238 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 7, i32 0, i32 1, i32 2>239 ret <4 x i32> %0240; CHECK-BE-LABEL: @check_be_swap_vec_sldwi_va_vb_3241; CHECK-BE: xxsldwi 34, 35, 34, 3242; CHECK-BE: blr243}244 245define <4 x i32> @check_be_vec_sldwi_va_undef_0(<4 x i32> %VA) {246entry:247 %0 = shufflevector <4 x i32> %VA, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>248 ret <4 x i32> %0249; CHECK-LE-LABEL: @check_be_vec_sldwi_va_undef_0250; CHECK-BE: blr251}252 253define <4 x i32> @check_be_vec_sldwi_va_undef_1(<4 x i32> %VA) {254entry:255 %0 = shufflevector <4 x i32> %VA, <4 x i32> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0>256 ret <4 x i32> %0257; CHECK-BE-LABEL: @check_be_vec_sldwi_va_undef_1258; CHECK-BE: xxsldwi 34, 34, 34, 1259; CHECK-BE: blr260}261 262define <4 x i32> @check_be_vec_sldwi_va_undef_2(<4 x i32> %VA) {263entry:264 %0 = shufflevector <4 x i32> %VA, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 0, i32 1>265 ret <4 x i32> %0266; CHECK-BE-LABEL: @check_be_vec_sldwi_va_undef_2267; CHECK-BE: xxswapd 34, 34268; CHECK-BE: blr269}270 271define <4 x i32> @check_be_vec_sldwi_va_undef_3(<4 x i32> %VA) {272entry:273 %0 = shufflevector <4 x i32> %VA, <4 x i32> undef, <4 x i32> <i32 3, i32 0, i32 1, i32 2>274 ret <4 x i32> %0275; CHECK-BE-LABEL: @check_be_vec_sldwi_va_undef_3276; CHECK-BE: xxsldwi 34, 34, 34, 3277; CHECK-BE: blr278}279 280; More test cases to test different types of vector inputs281define <16 x i8> @test_le_vec_sldwi_v16i8_v16i8(<16 x i8> %VA, <16 x i8> %VB) {282 entry:283 %0 = shufflevector <16 x i8> %VA, <16 x i8> %VB,<16 x i32> <i32 28, i32 29, i32 30, i32 31,i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>284 ret <16 x i8> %0285; CHECK-LE-LABEL: @test_le_vec_sldwi_v16i8_v16i8286; CHECK-LE: xxsldwi 34, 34, 35, 1287; CHECK-LE: blr288}289 290define <8 x i16> @test_le_vec_sldwi_v8i16_v8i16(<8 x i16> %VA, <8 x i16> %VB) {291 entry:292 %0 = shufflevector <8 x i16> %VA, <8 x i16> %VB,<8 x i32> <i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5>293 ret <8 x i16> %0294; CHECK-LE-LABEL: @test_le_vec_sldwi_v8i16_v8i16295; CHECK-LE: xxsldwi 34, 34, 35, 1296; CHECK-LE: blr297}298 299; Note here xxpermdi 34, 34, 35, 2 <=> xxsldwi 34, 34, 35, 2300define <2 x i64> @test_be_vec_sldwi_v2i64_v2i64(<2 x i64> %VA, <2 x i64> %VB) {301 entry:302 %0 = shufflevector <2 x i64> %VA, <2 x i64> %VB,<2 x i32> <i32 3, i32 0>303 ret <2 x i64> %0304; CHECK-LE-LABEL: @test_be_vec_sldwi_v2i64_v2i64305; CHECK-LE: xxpermdi 34, 34, 35, 2306; CHECK-LE: blr307}308