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1; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | \2; RUN: FileCheck %s -check-prefix=CHECK-LE3; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | \4; RUN: FileCheck %s -check-prefix=CHECK-BE5 6; Possible LE ShuffleVector masks (Case 1):7; ShuffleVector((vector double)a, (vector double)b, 3, 1)8; ShuffleVector((vector double)a, (vector double)b, 2, 1)9; ShuffleVector((vector double)a, (vector double)b, 3, 0)10; ShuffleVector((vector double)a, (vector double)b, 2, 0)11; which targets at:12; xxpermdi a, b, 013; xxpermdi a, b, 114; xxpermdi a, b, 215; xxpermdi a, b, 316; Possible LE Swap ShuffleVector masks (Case 2):17; ShuffleVector((vector double)a, (vector double)b, 1, 3)18; ShuffleVector((vector double)a, (vector double)b, 0, 3)19; ShuffleVector((vector double)a, (vector double)b, 1, 2)20; ShuffleVector((vector double)a, (vector double)b, 0, 2)21; which targets at:22; xxpermdi b, a, 023; xxpermdi b, a, 124; xxpermdi b, a, 225; xxpermdi b, a, 326; Possible LE ShuffleVector masks when a == b, b is undef (Case 3):27; ShuffleVector((vector double)a, (vector double)a, 1, 1)28; ShuffleVector((vector double)a, (vector double)a, 0, 1)29; ShuffleVector((vector double)a, (vector double)a, 1, 0)30; ShuffleVector((vector double)a, (vector double)a, 0, 0)31; which targets at:32; xxpermdi a, a, 033; xxpermdi a, a, 134; xxpermdi a, a, 235; xxpermdi a, a, 336 37; Possible BE ShuffleVector masks (Case 4):38; ShuffleVector((vector double)a, (vector double)b, 0, 2)39; ShuffleVector((vector double)a, (vector double)b, 0, 3)40; ShuffleVector((vector double)a, (vector double)b, 1, 2)41; ShuffleVector((vector double)a, (vector double)b, 1, 3)42; which targets at:43; xxpermdi a, b, 044; xxpermdi a, b, 145; xxpermdi a, b, 246; xxpermdi a, b, 347; Possible BE Swap ShuffleVector masks (Case 5):48; ShuffleVector((vector double)a, (vector double)b, 2, 0)49; ShuffleVector((vector double)a, (vector double)b, 3, 0)50; ShuffleVector((vector double)a, (vector double)b, 2, 1)51; ShuffleVector((vector double)a, (vector double)b, 3, 1)52; which targets at:53; xxpermdi b, a, 054; xxpermdi b, a, 155; xxpermdi b, a, 256; xxpermdi b, a, 357; Possible BE ShuffleVector masks when a == b, b is undef (Case 6):58; ShuffleVector((vector double)a, (vector double)a, 0, 0)59; ShuffleVector((vector double)a, (vector double)a, 0, 1)60; ShuffleVector((vector double)a, (vector double)a, 1, 0)61; ShuffleVector((vector double)a, (vector double)a, 1, 1)62; which targets at:63; xxpermdi a, a, 064; xxpermdi a, a, 165; xxpermdi a, a, 266; xxpermdi a, a, 367 68define <2 x double> @test_le_vec_xxpermdi_v2f64_v2f64_0(<2 x double> %VA, <2 x double> %VB) {69 entry:70 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 3, i32 1>71 ret <2 x double> %072; CHECK-LE-LABEL: @test_le_vec_xxpermdi_v2f64_v2f64_073; CHECK-LE: xxmrghd 34, 34, 3574; CHECK-LE: blr75}76 77define <2 x double> @test_le_vec_xxpermdi_v2f64_v2f64_1(<2 x double> %VA, <2 x double> %VB) {78 entry:79 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 2, i32 1>80 ret <2 x double> %081; CHECK-LE-LABEL: @test_le_vec_xxpermdi_v2f64_v2f64_182; CHECK-LE: xxpermdi 34, 34, 35, 183; CHECK-LE: blr84}85 86define <2 x double> @test_le_vec_xxpermdi_v2f64_v2f64_2(<2 x double> %VA, <2 x double> %VB) {87 entry:88 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 3, i32 0>89 ret <2 x double> %090; CHECK-LE-LABEL: @test_le_vec_xxpermdi_v2f64_v2f64_291; CHECK-LE: xxpermdi 34, 34, 35, 292; CHECK-LE: blr93}94 95define <2 x double> @test_le_vec_xxpermdi_v2f64_v2f64_3(<2 x double> %VA, <2 x double> %VB) {96 entry:97 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 2, i32 0>98 ret <2 x double> %099; CHECK-LE-LABEL: @test_le_vec_xxpermdi_v2f64_v2f64_3100; CHECK-LE: xxmrgld 34, 34, 35101; CHECK-LE: blr102}103 104define <2 x double> @test_le_swap_vec_xxpermdi_v2f64_v2f64_0(<2 x double> %VA, <2 x double> %VB) {105 entry:106 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 1, i32 3>107 ret <2 x double> %0108; CHECK-LE-LABEL: @test_le_swap_vec_xxpermdi_v2f64_v2f64_0109; CHECK-LE: xxmrghd 34, 35, 34110; CHECK-LE: blr111}112 113define <2 x double> @test_le_swap_vec_xxpermdi_v2f64_v2f64_1(<2 x double> %VA, <2 x double> %VB) {114 entry:115 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 0, i32 3>116 ret <2 x double> %0117; CHECK-LE-LABEL: @test_le_swap_vec_xxpermdi_v2f64_v2f64_1118; CHECK-LE: xxpermdi 34, 35, 34, 1119; CHECK-LE: blr120}121 122define <2 x double> @test_le_swap_vec_xxpermdi_v2f64_v2f64_2(<2 x double> %VA, <2 x double> %VB) {123 entry:124 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 1, i32 2>125 ret <2 x double> %0126; CHECK-LE-LABEL: @test_le_swap_vec_xxpermdi_v2f64_v2f64_2127; CHECK-LE: xxpermdi 34, 35, 34, 2128; CHECK-LE: blr129}130 131define <2 x double> @test_le_swap_vec_xxpermdi_v2f64_v2f64_3(<2 x double> %VA, <2 x double> %VB) {132 entry:133 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 0, i32 2>134 ret <2 x double> %0135; CHECK-LE-LABEL: @test_le_swap_vec_xxpermdi_v2f64_v2f64_3136; CHECK-LE: xxmrgld 34, 35, 34137; CHECK-LE: blr138}139 140define <2 x double> @test_le_vec_xxpermdi_v2f64_undef_0(<2 x double> %VA) {141 entry:142 %0 = shufflevector <2 x double> %VA, <2 x double> undef, <2 x i32> <i32 1, i32 1>143 ret <2 x double> %0144; CHECK-LE-LABEL: @test_le_vec_xxpermdi_v2f64_undef_0145; CHECK-LE: xxspltd 34, 34, 0146; CHECK-LE: blr147}148 149define <2 x double> @test_le_vec_xxpermdi_v2f64_undef_1(<2 x double> %VA) {150 entry:151 %0 = shufflevector <2 x double> %VA, <2 x double> undef, <2 x i32> <i32 0, i32 1>152 ret <2 x double> %0153; CHECK-LE-LABEL: @test_le_vec_xxpermdi_v2f64_undef_1154; CHECK-LE: blr155}156 157define <2 x double> @test_le_vec_xxpermdi_v2f64_undef_2(<2 x double> %VA) {158 entry:159 %0 = shufflevector <2 x double> %VA, <2 x double> undef, <2 x i32> <i32 1, i32 0>160 ret <2 x double> %0161; CHECK-LE-LABEL: @test_le_vec_xxpermdi_v2f64_undef_2162; CHECK-LE: xxswapd 34, 34163}164 165define <2 x double> @test_le_vec_xxpermdi_v2f64_undef_3(<2 x double> %VA) {166 entry:167 %0 = shufflevector <2 x double> %VA, <2 x double> undef, <2 x i32> <i32 0, i32 0>168 ret <2 x double> %0169; CHECK-LE-LABEL: @test_le_vec_xxpermdi_v2f64_undef_3170; CHECK-LE: xxspltd 34, 34, 1171; CHECK-LE: blr172}173 174; Start testing BE175define <2 x double> @test_be_vec_xxpermdi_v2f64_v2f64_0(<2 x double> %VA, <2 x double> %VB) {176 entry:177 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 0, i32 2>178 ret <2 x double> %0179; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v2f64_v2f64_0180; CHECK-BE: xxmrghd 34, 34, 35181; CHECK-BE: blr182}183 184define <2 x double> @test_be_vec_xxpermdi_v2f64_v2f64_1(<2 x double> %VA, <2 x double> %VB) {185 entry:186 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 0, i32 3>187 ret <2 x double> %0188; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v2f64_v2f64_1189; CHECK-BE: xxpermdi 34, 34, 35, 1190; CHECK-BE: blr191}192 193define <2 x double> @test_be_vec_xxpermdi_v2f64_v2f64_2(<2 x double> %VA, <2 x double> %VB) {194 entry:195 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 1, i32 2>196 ret <2 x double> %0197; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v2f64_v2f64_2198; CHECK-BE: xxpermdi 34, 34, 35, 2199; CHECK-BE: blr200}201 202define <2 x double> @test_be_vec_xxpermdi_v2f64_v2f64_3(<2 x double> %VA, <2 x double> %VB) {203 entry:204 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 1, i32 3>205 ret <2 x double> %0206; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v2f64_v2f64_3207; CHECK-BE: xxmrgld 34, 34, 35208; CHECK-BE: blr209}210 211define <2 x double> @test_be_swap_vec_xxpermdi_v2f64_v2f64_0(<2 x double> %VA, <2 x double> %VB) {212 entry:213 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 2, i32 0>214 ret <2 x double> %0215; CHECK-BE-LABEL: @test_be_swap_vec_xxpermdi_v2f64_v2f64_0216; CHECK-BE: xxmrghd 34, 35, 34217; CHECK-BE: blr218}219 220define <2 x double> @test_be_swap_vec_xxpermdi_v2f64_v2f64_1(<2 x double> %VA, <2 x double> %VB) {221 entry:222 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 2, i32 1>223 ret <2 x double> %0224; CHECK-BE-LABEL: @test_be_swap_vec_xxpermdi_v2f64_v2f64_1225; CHECK-BE: xxpermdi 34, 35, 34, 1226; CHECK-BE: blr227}228 229define <2 x double> @test_be_swap_vec_xxpermdi_v2f64_v2f64_2(<2 x double> %VA, <2 x double> %VB) {230 entry:231 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 3, i32 0>232 ret <2 x double> %0233; CHECK-BE-LABEL: @test_be_swap_vec_xxpermdi_v2f64_v2f64_2234; CHECK-BE: xxpermdi 34, 35, 34, 2235; CHECK-BE: blr236}237 238define <2 x double> @test_be_swap_vec_xxpermdi_v2f64_v2f64_3(<2 x double> %VA, <2 x double> %VB) {239 entry:240 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 3, i32 1>241 ret <2 x double> %0242; CHECK-BE-LABEL: @test_be_swap_vec_xxpermdi_v2f64_v2f64_3243; CHECK-BE: xxmrgld 34, 35, 34244; CHECK-BE: blr245}246 247define <2 x double> @test_be_vec_xxpermdi_v2f64_undef_0(<2 x double> %VA) {248 entry:249 %0 = shufflevector <2 x double> %VA, <2 x double> undef, <2 x i32> <i32 0, i32 0>250 ret <2 x double> %0251; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v2f64_undef_0252; CHECK-BE: xxspltd 34, 34, 0253; CHECK-BE: blr254}255 256define <2 x double> @test_be_vec_xxpermdi_v2f64_undef_1(<2 x double> %VA) {257 entry:258 %0 = shufflevector <2 x double> %VA, <2 x double> undef, <2 x i32> <i32 0, i32 1>259 ret <2 x double> %0260; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v2f64_undef_1261; CHECK-BE: blr262}263 264define <2 x double> @test_be_vec_xxpermdi_v2f64_undef_2(<2 x double> %VA) {265 entry:266 %0 = shufflevector <2 x double> %VA, <2 x double> undef, <2 x i32> <i32 1, i32 0>267 ret <2 x double> %0268; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v2f64_undef_2269; CHECK-LE: xxswapd 34, 34270}271 272define <2 x double> @test_be_vec_xxpermdi_v2f64_undef_3(<2 x double> %VA) {273 entry:274 %0 = shufflevector <2 x double> %VA, <2 x double> undef, <2 x i32> <i32 1, i32 1>275 ret <2 x double> %0276; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v2f64_undef_3277; CHECK-BE: xxspltd 34, 34, 1278; CHECK-BE: blr279}280 281; More test cases to test different types of vector inputs282define <16 x i8> @test_be_vec_xxpermdi_v16i8_v16i8(<16 x i8> %VA, <16 x i8> %VB) {283 entry:284 %0 = shufflevector <16 x i8> %VA, <16 x i8> %VB,<16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19>285 ret <16 x i8> %0286; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v16i8_v16i8287; CHECK-BE: xxpermdi 34, 34, 35, 1288; CHECK-BE: blr289}290 291define <8 x i16> @test_le_swap_vec_xxpermdi_v8i16_v8i16(<8 x i16> %VA, <8 x i16> %VB) {292 entry:293 %0 = shufflevector <8 x i16> %VA, <8 x i16> %VB,<8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>294 ret <8 x i16> %0295; CHECK-LE-LABEL: @test_le_swap_vec_xxpermdi_v8i16_v8i16296; CHECK-LE: xxpermdi 34, 35, 34, 1297; CHECK-LE: blr298}299 300define <4 x i32> @test_le_swap_vec_xxpermdi_v4i32_v4i32(<4 x i32> %VA, <4 x i32> %VB) {301 entry:302 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB,<4 x i32> <i32 0, i32 1, i32 6, i32 7>303 ret <4 x i32> %0304; CHECK-LE-LABEL: @test_le_swap_vec_xxpermdi_v4i32_v4i32305; CHECK-LE: xxpermdi 34, 35, 34, 1306; CHECK-LE: blr307}308