174 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \3; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-P94; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \5; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-P96; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \7; RUN: -mcpu=pwr9 -mattr=-altivec < %s | FileCheck %s \8; RUN: --check-prefix=CHECK-P9-NOALTIVEC9; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \10; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-P811 12define <4 x i32> @test_vextsh2w(<4 x i32> %m) {13; CHECK-P9-LABEL: test_vextsh2w:14; CHECK-P9: # %bb.0: # %entry15; CHECK-P9-NEXT: vextsh2w 2, 216; CHECK-P9-NEXT: blr17;18; CHECK-P9-NOALTIVEC-LABEL: test_vextsh2w:19; CHECK-P9-NOALTIVEC: # %bb.0: # %entry20; CHECK-P9-NOALTIVEC-NEXT: extsh 6, 621; CHECK-P9-NOALTIVEC-NEXT: extsh 5, 522; CHECK-P9-NOALTIVEC-NEXT: extsh 4, 423; CHECK-P9-NOALTIVEC-NEXT: extsh 3, 324; CHECK-P9-NOALTIVEC-NEXT: blr25;26; CHECK-P8-LABEL: test_vextsh2w:27; CHECK-P8: # %bb.0: # %entry28; CHECK-P8-NEXT: vspltisw 3, 829; CHECK-P8-NEXT: vadduwm 3, 3, 330; CHECK-P8-NEXT: vslw 2, 2, 331; CHECK-P8-NEXT: vsraw 2, 2, 332; CHECK-P8-NEXT: blr33entry:34 %shl = shl <4 x i32> %m, <i32 16, i32 16, i32 16, i32 16>35 %shr = ashr exact <4 x i32> %shl, <i32 16, i32 16, i32 16, i32 16>36 ret <4 x i32> %shr37}38 39define <4 x i32> @test_vextsb2w(<4 x i32> %m) {40; CHECK-P9-LABEL: test_vextsb2w:41; CHECK-P9: # %bb.0: # %entry42; CHECK-P9-NEXT: vextsb2w 2, 243; CHECK-P9-NEXT: blr44;45; CHECK-P9-NOALTIVEC-LABEL: test_vextsb2w:46; CHECK-P9-NOALTIVEC: # %bb.0: # %entry47; CHECK-P9-NOALTIVEC-NEXT: extsb 6, 648; CHECK-P9-NOALTIVEC-NEXT: extsb 5, 549; CHECK-P9-NOALTIVEC-NEXT: extsb 4, 450; CHECK-P9-NOALTIVEC-NEXT: extsb 3, 351; CHECK-P9-NOALTIVEC-NEXT: blr52;53; CHECK-P8-LABEL: test_vextsb2w:54; CHECK-P8: # %bb.0: # %entry55; CHECK-P8-NEXT: vspltisw 3, 1256; CHECK-P8-NEXT: vadduwm 3, 3, 357; CHECK-P8-NEXT: vslw 2, 2, 358; CHECK-P8-NEXT: vsraw 2, 2, 359; CHECK-P8-NEXT: blr60entry:61 %shl = shl <4 x i32> %m, <i32 24, i32 24, i32 24, i32 24>62 %shr = ashr exact <4 x i32> %shl, <i32 24, i32 24, i32 24, i32 24>63 ret <4 x i32> %shr64}65 66define <2 x i64> @test_vextsb2d(<2 x i64> %m) {67; CHECK-P9-LABEL: test_vextsb2d:68; CHECK-P9: # %bb.0: # %entry69; CHECK-P9-NEXT: vextsb2d 2, 270; CHECK-P9-NEXT: blr71;72; CHECK-P9-NOALTIVEC-LABEL: test_vextsb2d:73; CHECK-P9-NOALTIVEC: # %bb.0: # %entry74; CHECK-P9-NOALTIVEC-NEXT: extsb 3, 375; CHECK-P9-NOALTIVEC-NEXT: extsb 4, 476; CHECK-P9-NOALTIVEC-NEXT: blr77;78; CHECK-P8-LABEL: test_vextsb2d:79; CHECK-P8: # %bb.0: # %entry80; CHECK-P8-NEXT: addis 3, 2, .LCPI2_0@toc@ha81; CHECK-P8-NEXT: addi 3, 3, .LCPI2_0@toc@l82; CHECK-P8-NEXT: lxvd2x 35, 0, 383; CHECK-P8-NEXT: vsld 2, 2, 384; CHECK-P8-NEXT: vsrad 2, 2, 385; CHECK-P8-NEXT: blr86entry:87 %shl = shl <2 x i64> %m, <i64 56, i64 56>88 %shr = ashr exact <2 x i64> %shl, <i64 56, i64 56>89 ret <2 x i64> %shr90}91 92define <2 x i64> @test_vextsh2d(<2 x i64> %m) {93; CHECK-P9-LABEL: test_vextsh2d:94; CHECK-P9: # %bb.0: # %entry95; CHECK-P9-NEXT: vextsh2d 2, 296; CHECK-P9-NEXT: blr97;98; CHECK-P9-NOALTIVEC-LABEL: test_vextsh2d:99; CHECK-P9-NOALTIVEC: # %bb.0: # %entry100; CHECK-P9-NOALTIVEC-NEXT: extsh 3, 3101; CHECK-P9-NOALTIVEC-NEXT: extsh 4, 4102; CHECK-P9-NOALTIVEC-NEXT: blr103;104; CHECK-P8-LABEL: test_vextsh2d:105; CHECK-P8: # %bb.0: # %entry106; CHECK-P8-NEXT: addis 3, 2, .LCPI3_0@toc@ha107; CHECK-P8-NEXT: addi 3, 3, .LCPI3_0@toc@l108; CHECK-P8-NEXT: lxvd2x 35, 0, 3109; CHECK-P8-NEXT: vsld 2, 2, 3110; CHECK-P8-NEXT: vsrad 2, 2, 3111; CHECK-P8-NEXT: blr112entry:113 %shl = shl <2 x i64> %m, <i64 48, i64 48>114 %shr = ashr exact <2 x i64> %shl, <i64 48, i64 48>115 ret <2 x i64> %shr116}117 118define <2 x i64> @test_vextsw2d(<2 x i64> %m) {119; CHECK-P9-LABEL: test_vextsw2d:120; CHECK-P9: # %bb.0: # %entry121; CHECK-P9-NEXT: vextsw2d 2, 2122; CHECK-P9-NEXT: blr123;124; CHECK-P9-NOALTIVEC-LABEL: test_vextsw2d:125; CHECK-P9-NOALTIVEC: # %bb.0: # %entry126; CHECK-P9-NOALTIVEC-NEXT: extsw 3, 3127; CHECK-P9-NOALTIVEC-NEXT: extsw 4, 4128; CHECK-P9-NOALTIVEC-NEXT: blr129;130; CHECK-P8-LABEL: test_vextsw2d:131; CHECK-P8: # %bb.0: # %entry132; CHECK-P8-NEXT: addis 3, 2, .LCPI4_0@toc@ha133; CHECK-P8-NEXT: addi 3, 3, .LCPI4_0@toc@l134; CHECK-P8-NEXT: lxvd2x 35, 0, 3135; CHECK-P8-NEXT: vsld 2, 2, 3136; CHECK-P8-NEXT: vsrad 2, 2, 3137; CHECK-P8-NEXT: blr138entry:139 %shl = shl <2 x i64> %m, <i64 32, i64 32>140 %shr = ashr exact <2 x i64> %shl, <i64 32, i64 32>141 ret <2 x i64> %shr142}143 144define <2 x i64> @test_none(<2 x i64> %m) {145; CHECK-P9-LABEL: test_none:146; CHECK-P9: # %bb.0: # %entry147; CHECK-P9-NEXT: xxspltib 35, 16148; CHECK-P9-NEXT: vextsb2d 3, 3149; CHECK-P9-NEXT: vsld 2, 2, 3150; CHECK-P9-NEXT: vsrad 2, 2, 3151; CHECK-P9-NEXT: blr152;153; CHECK-P9-NOALTIVEC-LABEL: test_none:154; CHECK-P9-NOALTIVEC: # %bb.0: # %entry155; CHECK-P9-NOALTIVEC-NEXT: sldi 3, 3, 16156; CHECK-P9-NOALTIVEC-NEXT: sldi 4, 4, 16157; CHECK-P9-NOALTIVEC-NEXT: sradi 3, 3, 16158; CHECK-P9-NOALTIVEC-NEXT: sradi 4, 4, 16159; CHECK-P9-NOALTIVEC-NEXT: blr160;161; CHECK-P8-LABEL: test_none:162; CHECK-P8: # %bb.0: # %entry163; CHECK-P8-NEXT: addis 3, 2, .LCPI5_0@toc@ha164; CHECK-P8-NEXT: addi 3, 3, .LCPI5_0@toc@l165; CHECK-P8-NEXT: lxvd2x 35, 0, 3166; CHECK-P8-NEXT: vsld 2, 2, 3167; CHECK-P8-NEXT: vsrad 2, 2, 3168; CHECK-P8-NEXT: blr169entry:170 %shl = shl <2 x i64> %m, <i64 16, i64 16>171 %shr = ashr exact <2 x i64> %shl, <i64 16, i64 16>172 ret <2 x i64> %shr173}174