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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \3; RUN: -mcpu=pwr9 -mtriple=powerpc64le < %s | FileCheck %s --check-prefix=PWR9LE4; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \5; RUN: -mcpu=pwr9 -mtriple=powerpc64 < %s | FileCheck %s --check-prefix=PWR9BE6; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \7; RUN: -mcpu=pwr10 -mtriple=powerpc64le < %s | FileCheck %s --check-prefix=PWR10LE8; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \9; RUN: -mcpu=pwr10 -mtriple=powerpc64 < %s | FileCheck %s --check-prefix=PWR10BE10 11define dso_local i32 @v2i32(<2 x i32> %a) local_unnamed_addr #0 {12; PWR9LE-LABEL: v2i32:13; PWR9LE: # %bb.0: # %entry14; PWR9LE-NEXT: xxspltw v3, v2, 215; PWR9LE-NEXT: li r3, 016; PWR9LE-NEXT: vmuluwm v2, v2, v317; PWR9LE-NEXT: vextuwrx r3, r3, v218; PWR9LE-NEXT: blr19;20; PWR9BE-LABEL: v2i32:21; PWR9BE: # %bb.0: # %entry22; PWR9BE-NEXT: xxspltw v3, v2, 123; PWR9BE-NEXT: li r3, 024; PWR9BE-NEXT: vmuluwm v2, v2, v325; PWR9BE-NEXT: vextuwlx r3, r3, v226; PWR9BE-NEXT: blr27;28; PWR10LE-LABEL: v2i32:29; PWR10LE: # %bb.0: # %entry30; PWR10LE-NEXT: xxspltw v3, v2, 231; PWR10LE-NEXT: li r3, 032; PWR10LE-NEXT: vmuluwm v2, v2, v333; PWR10LE-NEXT: vextuwrx r3, r3, v234; PWR10LE-NEXT: blr35;36; PWR10BE-LABEL: v2i32:37; PWR10BE: # %bb.0: # %entry38; PWR10BE-NEXT: xxspltw v3, v2, 139; PWR10BE-NEXT: li r3, 040; PWR10BE-NEXT: vmuluwm v2, v2, v341; PWR10BE-NEXT: vextuwlx r3, r3, v242; PWR10BE-NEXT: blr43entry:44 %0 = call i32 @llvm.vector.reduce.mul.v2i32(<2 x i32> %a)45 ret i32 %046}47 48define dso_local i32 @v4i32(<4 x i32> %a) local_unnamed_addr #0 {49; PWR9LE-LABEL: v4i32:50; PWR9LE: # %bb.0: # %entry51; PWR9LE-NEXT: xxswapd v3, v252; PWR9LE-NEXT: li r3, 053; PWR9LE-NEXT: vmuluwm v2, v2, v354; PWR9LE-NEXT: xxspltw v3, v2, 255; PWR9LE-NEXT: vmuluwm v2, v2, v356; PWR9LE-NEXT: vextuwrx r3, r3, v257; PWR9LE-NEXT: blr58;59; PWR9BE-LABEL: v4i32:60; PWR9BE: # %bb.0: # %entry61; PWR9BE-NEXT: xxswapd v3, v262; PWR9BE-NEXT: li r3, 063; PWR9BE-NEXT: vmuluwm v2, v2, v364; PWR9BE-NEXT: xxspltw v3, v2, 165; PWR9BE-NEXT: vmuluwm v2, v2, v366; PWR9BE-NEXT: vextuwlx r3, r3, v267; PWR9BE-NEXT: blr68;69; PWR10LE-LABEL: v4i32:70; PWR10LE: # %bb.0: # %entry71; PWR10LE-NEXT: xxswapd v3, v272; PWR10LE-NEXT: li r3, 073; PWR10LE-NEXT: vmuluwm v2, v2, v374; PWR10LE-NEXT: xxspltw v3, v2, 275; PWR10LE-NEXT: vmuluwm v2, v2, v376; PWR10LE-NEXT: vextuwrx r3, r3, v277; PWR10LE-NEXT: blr78;79; PWR10BE-LABEL: v4i32:80; PWR10BE: # %bb.0: # %entry81; PWR10BE-NEXT: xxswapd v3, v282; PWR10BE-NEXT: li r3, 083; PWR10BE-NEXT: vmuluwm v2, v2, v384; PWR10BE-NEXT: xxspltw v3, v2, 185; PWR10BE-NEXT: vmuluwm v2, v2, v386; PWR10BE-NEXT: vextuwlx r3, r3, v287; PWR10BE-NEXT: blr88entry:89 %0 = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> %a)90 ret i32 %091}92 93define dso_local i32 @v8i32(<8 x i32> %a) local_unnamed_addr #0 {94; PWR9LE-LABEL: v8i32:95; PWR9LE: # %bb.0: # %entry96; PWR9LE-NEXT: vmuluwm v2, v2, v397; PWR9LE-NEXT: li r3, 098; PWR9LE-NEXT: xxswapd v3, v299; PWR9LE-NEXT: vmuluwm v2, v2, v3100; PWR9LE-NEXT: xxspltw v3, v2, 2101; PWR9LE-NEXT: vmuluwm v2, v2, v3102; PWR9LE-NEXT: vextuwrx r3, r3, v2103; PWR9LE-NEXT: blr104;105; PWR9BE-LABEL: v8i32:106; PWR9BE: # %bb.0: # %entry107; PWR9BE-NEXT: vmuluwm v2, v2, v3108; PWR9BE-NEXT: li r3, 0109; PWR9BE-NEXT: xxswapd v3, v2110; PWR9BE-NEXT: vmuluwm v2, v2, v3111; PWR9BE-NEXT: xxspltw v3, v2, 1112; PWR9BE-NEXT: vmuluwm v2, v2, v3113; PWR9BE-NEXT: vextuwlx r3, r3, v2114; PWR9BE-NEXT: blr115;116; PWR10LE-LABEL: v8i32:117; PWR10LE: # %bb.0: # %entry118; PWR10LE-NEXT: vmuluwm v2, v2, v3119; PWR10LE-NEXT: li r3, 0120; PWR10LE-NEXT: xxswapd v3, v2121; PWR10LE-NEXT: vmuluwm v2, v2, v3122; PWR10LE-NEXT: xxspltw v3, v2, 2123; PWR10LE-NEXT: vmuluwm v2, v2, v3124; PWR10LE-NEXT: vextuwrx r3, r3, v2125; PWR10LE-NEXT: blr126;127; PWR10BE-LABEL: v8i32:128; PWR10BE: # %bb.0: # %entry129; PWR10BE-NEXT: vmuluwm v2, v2, v3130; PWR10BE-NEXT: li r3, 0131; PWR10BE-NEXT: xxswapd v3, v2132; PWR10BE-NEXT: vmuluwm v2, v2, v3133; PWR10BE-NEXT: xxspltw v3, v2, 1134; PWR10BE-NEXT: vmuluwm v2, v2, v3135; PWR10BE-NEXT: vextuwlx r3, r3, v2136; PWR10BE-NEXT: blr137entry:138 %0 = call i32 @llvm.vector.reduce.mul.v8i32(<8 x i32> %a)139 ret i32 %0140}141 142define dso_local i32 @v16i32(<16 x i32> %a) local_unnamed_addr #0 {143; PWR9LE-LABEL: v16i32:144; PWR9LE: # %bb.0: # %entry145; PWR9LE-NEXT: vmuluwm v3, v3, v5146; PWR9LE-NEXT: vmuluwm v2, v2, v4147; PWR9LE-NEXT: li r3, 0148; PWR9LE-NEXT: vmuluwm v2, v2, v3149; PWR9LE-NEXT: xxswapd v3, v2150; PWR9LE-NEXT: vmuluwm v2, v2, v3151; PWR9LE-NEXT: xxspltw v3, v2, 2152; PWR9LE-NEXT: vmuluwm v2, v2, v3153; PWR9LE-NEXT: vextuwrx r3, r3, v2154; PWR9LE-NEXT: blr155;156; PWR9BE-LABEL: v16i32:157; PWR9BE: # %bb.0: # %entry158; PWR9BE-NEXT: vmuluwm v3, v3, v5159; PWR9BE-NEXT: vmuluwm v2, v2, v4160; PWR9BE-NEXT: li r3, 0161; PWR9BE-NEXT: vmuluwm v2, v2, v3162; PWR9BE-NEXT: xxswapd v3, v2163; PWR9BE-NEXT: vmuluwm v2, v2, v3164; PWR9BE-NEXT: xxspltw v3, v2, 1165; PWR9BE-NEXT: vmuluwm v2, v2, v3166; PWR9BE-NEXT: vextuwlx r3, r3, v2167; PWR9BE-NEXT: blr168;169; PWR10LE-LABEL: v16i32:170; PWR10LE: # %bb.0: # %entry171; PWR10LE-NEXT: vmuluwm v3, v3, v5172; PWR10LE-NEXT: vmuluwm v2, v2, v4173; PWR10LE-NEXT: li r3, 0174; PWR10LE-NEXT: vmuluwm v2, v2, v3175; PWR10LE-NEXT: xxswapd v3, v2176; PWR10LE-NEXT: vmuluwm v2, v2, v3177; PWR10LE-NEXT: xxspltw v3, v2, 2178; PWR10LE-NEXT: vmuluwm v2, v2, v3179; PWR10LE-NEXT: vextuwrx r3, r3, v2180; PWR10LE-NEXT: blr181;182; PWR10BE-LABEL: v16i32:183; PWR10BE: # %bb.0: # %entry184; PWR10BE-NEXT: vmuluwm v3, v3, v5185; PWR10BE-NEXT: vmuluwm v2, v2, v4186; PWR10BE-NEXT: li r3, 0187; PWR10BE-NEXT: vmuluwm v2, v2, v3188; PWR10BE-NEXT: xxswapd v3, v2189; PWR10BE-NEXT: vmuluwm v2, v2, v3190; PWR10BE-NEXT: xxspltw v3, v2, 1191; PWR10BE-NEXT: vmuluwm v2, v2, v3192; PWR10BE-NEXT: vextuwlx r3, r3, v2193; PWR10BE-NEXT: blr194entry:195 %0 = call i32 @llvm.vector.reduce.mul.v16i32(<16 x i32> %a)196 ret i32 %0197}198 199declare i32 @llvm.vector.reduce.mul.v2i32(<2 x i32>) #0200declare i32 @llvm.vector.reduce.mul.v4i32(<4 x i32>) #0201declare i32 @llvm.vector.reduce.mul.v8i32(<8 x i32>) #0202declare i32 @llvm.vector.reduce.mul.v16i32(<16 x i32>) #0203 204attributes #0 = { nounwind }205