797 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \3; RUN: -mcpu=pwr9 -mtriple=powerpc64le < %s | FileCheck %s --check-prefix=PWR9LE4; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \5; RUN: -mcpu=pwr9 -mtriple=powerpc64 < %s | FileCheck %s --check-prefix=PWR9BE6; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \7; RUN: -mcpu=pwr10 -mtriple=powerpc64le < %s | FileCheck %s --check-prefix=PWR10LE8; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \9; RUN: -mcpu=pwr10 -mtriple=powerpc64 < %s | FileCheck %s --check-prefix=PWR10BE10 11;;12;; Vectors of type i813;;14define dso_local i8 @v2i8(<2 x i8> %a) local_unnamed_addr #0 {15; PWR9LE-LABEL: v2i8:16; PWR9LE: # %bb.0: # %entry17; PWR9LE-NEXT: vspltb v3, v2, 1418; PWR9LE-NEXT: li r3, 019; PWR9LE-NEXT: vmaxub v2, v2, v320; PWR9LE-NEXT: vextubrx r3, r3, v221; PWR9LE-NEXT: blr22;23; PWR9BE-LABEL: v2i8:24; PWR9BE: # %bb.0: # %entry25; PWR9BE-NEXT: vspltb v3, v2, 126; PWR9BE-NEXT: li r3, 027; PWR9BE-NEXT: vmaxub v2, v2, v328; PWR9BE-NEXT: vextublx r3, r3, v229; PWR9BE-NEXT: blr30;31; PWR10LE-LABEL: v2i8:32; PWR10LE: # %bb.0: # %entry33; PWR10LE-NEXT: vspltb v3, v2, 1434; PWR10LE-NEXT: li r3, 035; PWR10LE-NEXT: vmaxub v2, v2, v336; PWR10LE-NEXT: vextubrx r3, r3, v237; PWR10LE-NEXT: blr38;39; PWR10BE-LABEL: v2i8:40; PWR10BE: # %bb.0: # %entry41; PWR10BE-NEXT: vspltb v3, v2, 142; PWR10BE-NEXT: li r3, 043; PWR10BE-NEXT: vmaxub v2, v2, v344; PWR10BE-NEXT: vextublx r3, r3, v245; PWR10BE-NEXT: blr46entry:47 %0 = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> %a)48 ret i8 %049}50 51define dso_local i8 @v4i8(<4 x i8> %a) local_unnamed_addr #0 {52; PWR9LE-LABEL: v4i8:53; PWR9LE: # %bb.0: # %entry54; PWR9LE-NEXT: vsplth v3, v2, 655; PWR9LE-NEXT: li r3, 056; PWR9LE-NEXT: vmaxub v2, v2, v357; PWR9LE-NEXT: vspltb v3, v2, 1458; PWR9LE-NEXT: vmaxub v2, v2, v359; PWR9LE-NEXT: vextubrx r3, r3, v260; PWR9LE-NEXT: blr61;62; PWR9BE-LABEL: v4i8:63; PWR9BE: # %bb.0: # %entry64; PWR9BE-NEXT: vsplth v3, v2, 165; PWR9BE-NEXT: li r3, 066; PWR9BE-NEXT: vmaxub v2, v2, v367; PWR9BE-NEXT: vspltb v3, v2, 168; PWR9BE-NEXT: vmaxub v2, v2, v369; PWR9BE-NEXT: vextublx r3, r3, v270; PWR9BE-NEXT: blr71;72; PWR10LE-LABEL: v4i8:73; PWR10LE: # %bb.0: # %entry74; PWR10LE-NEXT: vsplth v3, v2, 675; PWR10LE-NEXT: li r3, 076; PWR10LE-NEXT: vmaxub v2, v2, v377; PWR10LE-NEXT: vspltb v3, v2, 1478; PWR10LE-NEXT: vmaxub v2, v2, v379; PWR10LE-NEXT: vextubrx r3, r3, v280; PWR10LE-NEXT: blr81;82; PWR10BE-LABEL: v4i8:83; PWR10BE: # %bb.0: # %entry84; PWR10BE-NEXT: vsplth v3, v2, 185; PWR10BE-NEXT: li r3, 086; PWR10BE-NEXT: vmaxub v2, v2, v387; PWR10BE-NEXT: vspltb v3, v2, 188; PWR10BE-NEXT: vmaxub v2, v2, v389; PWR10BE-NEXT: vextublx r3, r3, v290; PWR10BE-NEXT: blr91entry:92 %0 = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> %a)93 ret i8 %094}95 96define dso_local i8 @v8i8(<8 x i8> %a) local_unnamed_addr #0 {97; PWR9LE-LABEL: v8i8:98; PWR9LE: # %bb.0: # %entry99; PWR9LE-NEXT: xxspltw v3, v2, 2100; PWR9LE-NEXT: li r3, 0101; PWR9LE-NEXT: vmaxub v2, v2, v3102; PWR9LE-NEXT: vsplth v3, v2, 6103; PWR9LE-NEXT: vmaxub v2, v2, v3104; PWR9LE-NEXT: vspltb v3, v2, 14105; PWR9LE-NEXT: vmaxub v2, v2, v3106; PWR9LE-NEXT: vextubrx r3, r3, v2107; PWR9LE-NEXT: blr108;109; PWR9BE-LABEL: v8i8:110; PWR9BE: # %bb.0: # %entry111; PWR9BE-NEXT: xxspltw v3, v2, 1112; PWR9BE-NEXT: li r3, 0113; PWR9BE-NEXT: vmaxub v2, v2, v3114; PWR9BE-NEXT: vsplth v3, v2, 1115; PWR9BE-NEXT: vmaxub v2, v2, v3116; PWR9BE-NEXT: vspltb v3, v2, 1117; PWR9BE-NEXT: vmaxub v2, v2, v3118; PWR9BE-NEXT: vextublx r3, r3, v2119; PWR9BE-NEXT: blr120;121; PWR10LE-LABEL: v8i8:122; PWR10LE: # %bb.0: # %entry123; PWR10LE-NEXT: xxspltw v3, v2, 2124; PWR10LE-NEXT: li r3, 0125; PWR10LE-NEXT: vmaxub v2, v2, v3126; PWR10LE-NEXT: vsplth v3, v2, 6127; PWR10LE-NEXT: vmaxub v2, v2, v3128; PWR10LE-NEXT: vspltb v3, v2, 14129; PWR10LE-NEXT: vmaxub v2, v2, v3130; PWR10LE-NEXT: vextubrx r3, r3, v2131; PWR10LE-NEXT: blr132;133; PWR10BE-LABEL: v8i8:134; PWR10BE: # %bb.0: # %entry135; PWR10BE-NEXT: xxspltw v3, v2, 1136; PWR10BE-NEXT: li r3, 0137; PWR10BE-NEXT: vmaxub v2, v2, v3138; PWR10BE-NEXT: vsplth v3, v2, 1139; PWR10BE-NEXT: vmaxub v2, v2, v3140; PWR10BE-NEXT: vspltb v3, v2, 1141; PWR10BE-NEXT: vmaxub v2, v2, v3142; PWR10BE-NEXT: vextublx r3, r3, v2143; PWR10BE-NEXT: blr144entry:145 %0 = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> %a)146 ret i8 %0147}148 149define dso_local i8 @v16i8(<16 x i8> %a) local_unnamed_addr #0 {150; PWR9LE-LABEL: v16i8:151; PWR9LE: # %bb.0: # %entry152; PWR9LE-NEXT: xxswapd v3, v2153; PWR9LE-NEXT: li r3, 0154; PWR9LE-NEXT: vmaxub v2, v2, v3155; PWR9LE-NEXT: xxspltw v3, v2, 2156; PWR9LE-NEXT: vmaxub v2, v2, v3157; PWR9LE-NEXT: vsplth v3, v2, 6158; PWR9LE-NEXT: vmaxub v2, v2, v3159; PWR9LE-NEXT: vspltb v3, v2, 14160; PWR9LE-NEXT: vmaxub v2, v2, v3161; PWR9LE-NEXT: vextubrx r3, r3, v2162; PWR9LE-NEXT: blr163;164; PWR9BE-LABEL: v16i8:165; PWR9BE: # %bb.0: # %entry166; PWR9BE-NEXT: xxswapd v3, v2167; PWR9BE-NEXT: li r3, 0168; PWR9BE-NEXT: vmaxub v2, v2, v3169; PWR9BE-NEXT: xxspltw v3, v2, 1170; PWR9BE-NEXT: vmaxub v2, v2, v3171; PWR9BE-NEXT: vsplth v3, v2, 1172; PWR9BE-NEXT: vmaxub v2, v2, v3173; PWR9BE-NEXT: vspltb v3, v2, 1174; PWR9BE-NEXT: vmaxub v2, v2, v3175; PWR9BE-NEXT: vextublx r3, r3, v2176; PWR9BE-NEXT: blr177;178; PWR10LE-LABEL: v16i8:179; PWR10LE: # %bb.0: # %entry180; PWR10LE-NEXT: xxswapd v3, v2181; PWR10LE-NEXT: li r3, 0182; PWR10LE-NEXT: vmaxub v2, v2, v3183; PWR10LE-NEXT: xxspltw v3, v2, 2184; PWR10LE-NEXT: vmaxub v2, v2, v3185; PWR10LE-NEXT: vsplth v3, v2, 6186; PWR10LE-NEXT: vmaxub v2, v2, v3187; PWR10LE-NEXT: vspltb v3, v2, 14188; PWR10LE-NEXT: vmaxub v2, v2, v3189; PWR10LE-NEXT: vextubrx r3, r3, v2190; PWR10LE-NEXT: blr191;192; PWR10BE-LABEL: v16i8:193; PWR10BE: # %bb.0: # %entry194; PWR10BE-NEXT: xxswapd v3, v2195; PWR10BE-NEXT: li r3, 0196; PWR10BE-NEXT: vmaxub v2, v2, v3197; PWR10BE-NEXT: xxspltw v3, v2, 1198; PWR10BE-NEXT: vmaxub v2, v2, v3199; PWR10BE-NEXT: vsplth v3, v2, 1200; PWR10BE-NEXT: vmaxub v2, v2, v3201; PWR10BE-NEXT: vspltb v3, v2, 1202; PWR10BE-NEXT: vmaxub v2, v2, v3203; PWR10BE-NEXT: vextublx r3, r3, v2204; PWR10BE-NEXT: blr205entry:206 %0 = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> %a)207 ret i8 %0208}209 210declare i8 @llvm.vector.reduce.umax.v2i8(<2 x i8>) #0211declare i8 @llvm.vector.reduce.umax.v4i8(<4 x i8>) #0212declare i8 @llvm.vector.reduce.umax.v8i8(<8 x i8>) #0213declare i8 @llvm.vector.reduce.umax.v16i8(<16 x i8>) #0214 215;;216;; Vectors of type i16217;;218define dso_local i16 @v2i16(<2 x i16> %a) local_unnamed_addr #0 {219; PWR9LE-LABEL: v2i16:220; PWR9LE: # %bb.0: # %entry221; PWR9LE-NEXT: vsplth v3, v2, 6222; PWR9LE-NEXT: li r3, 0223; PWR9LE-NEXT: vmaxuh v2, v2, v3224; PWR9LE-NEXT: vextuhrx r3, r3, v2225; PWR9LE-NEXT: blr226;227; PWR9BE-LABEL: v2i16:228; PWR9BE: # %bb.0: # %entry229; PWR9BE-NEXT: vsplth v3, v2, 1230; PWR9BE-NEXT: li r3, 0231; PWR9BE-NEXT: vmaxuh v2, v2, v3232; PWR9BE-NEXT: vextuhlx r3, r3, v2233; PWR9BE-NEXT: blr234;235; PWR10LE-LABEL: v2i16:236; PWR10LE: # %bb.0: # %entry237; PWR10LE-NEXT: vsplth v3, v2, 6238; PWR10LE-NEXT: li r3, 0239; PWR10LE-NEXT: vmaxuh v2, v2, v3240; PWR10LE-NEXT: vextuhrx r3, r3, v2241; PWR10LE-NEXT: blr242;243; PWR10BE-LABEL: v2i16:244; PWR10BE: # %bb.0: # %entry245; PWR10BE-NEXT: vsplth v3, v2, 1246; PWR10BE-NEXT: li r3, 0247; PWR10BE-NEXT: vmaxuh v2, v2, v3248; PWR10BE-NEXT: vextuhlx r3, r3, v2249; PWR10BE-NEXT: blr250entry:251 %0 = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> %a)252 ret i16 %0253}254 255define dso_local i16 @v4i16(<4 x i16> %a) local_unnamed_addr #0 {256; PWR9LE-LABEL: v4i16:257; PWR9LE: # %bb.0: # %entry258; PWR9LE-NEXT: xxspltw v3, v2, 2259; PWR9LE-NEXT: li r3, 0260; PWR9LE-NEXT: vmaxuh v2, v2, v3261; PWR9LE-NEXT: vsplth v3, v2, 6262; PWR9LE-NEXT: vmaxuh v2, v2, v3263; PWR9LE-NEXT: vextuhrx r3, r3, v2264; PWR9LE-NEXT: blr265;266; PWR9BE-LABEL: v4i16:267; PWR9BE: # %bb.0: # %entry268; PWR9BE-NEXT: xxspltw v3, v2, 1269; PWR9BE-NEXT: li r3, 0270; PWR9BE-NEXT: vmaxuh v2, v2, v3271; PWR9BE-NEXT: vsplth v3, v2, 1272; PWR9BE-NEXT: vmaxuh v2, v2, v3273; PWR9BE-NEXT: vextuhlx r3, r3, v2274; PWR9BE-NEXT: blr275;276; PWR10LE-LABEL: v4i16:277; PWR10LE: # %bb.0: # %entry278; PWR10LE-NEXT: xxspltw v3, v2, 2279; PWR10LE-NEXT: li r3, 0280; PWR10LE-NEXT: vmaxuh v2, v2, v3281; PWR10LE-NEXT: vsplth v3, v2, 6282; PWR10LE-NEXT: vmaxuh v2, v2, v3283; PWR10LE-NEXT: vextuhrx r3, r3, v2284; PWR10LE-NEXT: blr285;286; PWR10BE-LABEL: v4i16:287; PWR10BE: # %bb.0: # %entry288; PWR10BE-NEXT: xxspltw v3, v2, 1289; PWR10BE-NEXT: li r3, 0290; PWR10BE-NEXT: vmaxuh v2, v2, v3291; PWR10BE-NEXT: vsplth v3, v2, 1292; PWR10BE-NEXT: vmaxuh v2, v2, v3293; PWR10BE-NEXT: vextuhlx r3, r3, v2294; PWR10BE-NEXT: blr295entry:296 %0 = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> %a)297 ret i16 %0298}299 300define dso_local i16 @v8i16(<8 x i16> %a) local_unnamed_addr #0 {301; PWR9LE-LABEL: v8i16:302; PWR9LE: # %bb.0: # %entry303; PWR9LE-NEXT: xxswapd v3, v2304; PWR9LE-NEXT: li r3, 0305; PWR9LE-NEXT: vmaxuh v2, v2, v3306; PWR9LE-NEXT: xxspltw v3, v2, 2307; PWR9LE-NEXT: vmaxuh v2, v2, v3308; PWR9LE-NEXT: vsplth v3, v2, 6309; PWR9LE-NEXT: vmaxuh v2, v2, v3310; PWR9LE-NEXT: vextuhrx r3, r3, v2311; PWR9LE-NEXT: blr312;313; PWR9BE-LABEL: v8i16:314; PWR9BE: # %bb.0: # %entry315; PWR9BE-NEXT: xxswapd v3, v2316; PWR9BE-NEXT: li r3, 0317; PWR9BE-NEXT: vmaxuh v2, v2, v3318; PWR9BE-NEXT: xxspltw v3, v2, 1319; PWR9BE-NEXT: vmaxuh v2, v2, v3320; PWR9BE-NEXT: vsplth v3, v2, 1321; PWR9BE-NEXT: vmaxuh v2, v2, v3322; PWR9BE-NEXT: vextuhlx r3, r3, v2323; PWR9BE-NEXT: blr324;325; PWR10LE-LABEL: v8i16:326; PWR10LE: # %bb.0: # %entry327; PWR10LE-NEXT: xxswapd v3, v2328; PWR10LE-NEXT: li r3, 0329; PWR10LE-NEXT: vmaxuh v2, v2, v3330; PWR10LE-NEXT: xxspltw v3, v2, 2331; PWR10LE-NEXT: vmaxuh v2, v2, v3332; PWR10LE-NEXT: vsplth v3, v2, 6333; PWR10LE-NEXT: vmaxuh v2, v2, v3334; PWR10LE-NEXT: vextuhrx r3, r3, v2335; PWR10LE-NEXT: blr336;337; PWR10BE-LABEL: v8i16:338; PWR10BE: # %bb.0: # %entry339; PWR10BE-NEXT: xxswapd v3, v2340; PWR10BE-NEXT: li r3, 0341; PWR10BE-NEXT: vmaxuh v2, v2, v3342; PWR10BE-NEXT: xxspltw v3, v2, 1343; PWR10BE-NEXT: vmaxuh v2, v2, v3344; PWR10BE-NEXT: vsplth v3, v2, 1345; PWR10BE-NEXT: vmaxuh v2, v2, v3346; PWR10BE-NEXT: vextuhlx r3, r3, v2347; PWR10BE-NEXT: blr348entry:349 %0 = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> %a)350 ret i16 %0351}352 353define dso_local i16 @v16i16(<16 x i16> %a) local_unnamed_addr #0 {354; PWR9LE-LABEL: v16i16:355; PWR9LE: # %bb.0: # %entry356; PWR9LE-NEXT: vmaxuh v2, v2, v3357; PWR9LE-NEXT: li r3, 0358; PWR9LE-NEXT: xxswapd v3, v2359; PWR9LE-NEXT: vmaxuh v2, v2, v3360; PWR9LE-NEXT: xxspltw v3, v2, 2361; PWR9LE-NEXT: vmaxuh v2, v2, v3362; PWR9LE-NEXT: vsplth v3, v2, 6363; PWR9LE-NEXT: vmaxuh v2, v2, v3364; PWR9LE-NEXT: vextuhrx r3, r3, v2365; PWR9LE-NEXT: blr366;367; PWR9BE-LABEL: v16i16:368; PWR9BE: # %bb.0: # %entry369; PWR9BE-NEXT: vmaxuh v2, v2, v3370; PWR9BE-NEXT: li r3, 0371; PWR9BE-NEXT: xxswapd v3, v2372; PWR9BE-NEXT: vmaxuh v2, v2, v3373; PWR9BE-NEXT: xxspltw v3, v2, 1374; PWR9BE-NEXT: vmaxuh v2, v2, v3375; PWR9BE-NEXT: vsplth v3, v2, 1376; PWR9BE-NEXT: vmaxuh v2, v2, v3377; PWR9BE-NEXT: vextuhlx r3, r3, v2378; PWR9BE-NEXT: blr379;380; PWR10LE-LABEL: v16i16:381; PWR10LE: # %bb.0: # %entry382; PWR10LE-NEXT: vmaxuh v2, v2, v3383; PWR10LE-NEXT: li r3, 0384; PWR10LE-NEXT: xxswapd v3, v2385; PWR10LE-NEXT: vmaxuh v2, v2, v3386; PWR10LE-NEXT: xxspltw v3, v2, 2387; PWR10LE-NEXT: vmaxuh v2, v2, v3388; PWR10LE-NEXT: vsplth v3, v2, 6389; PWR10LE-NEXT: vmaxuh v2, v2, v3390; PWR10LE-NEXT: vextuhrx r3, r3, v2391; PWR10LE-NEXT: blr392;393; PWR10BE-LABEL: v16i16:394; PWR10BE: # %bb.0: # %entry395; PWR10BE-NEXT: vmaxuh v2, v2, v3396; PWR10BE-NEXT: li r3, 0397; PWR10BE-NEXT: xxswapd v3, v2398; PWR10BE-NEXT: vmaxuh v2, v2, v3399; PWR10BE-NEXT: xxspltw v3, v2, 1400; PWR10BE-NEXT: vmaxuh v2, v2, v3401; PWR10BE-NEXT: vsplth v3, v2, 1402; PWR10BE-NEXT: vmaxuh v2, v2, v3403; PWR10BE-NEXT: vextuhlx r3, r3, v2404; PWR10BE-NEXT: blr405entry:406 %0 = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> %a)407 ret i16 %0408}409 410declare i16 @llvm.vector.reduce.umax.v2i16(<2 x i16>) #0411declare i16 @llvm.vector.reduce.umax.v4i16(<4 x i16>) #0412declare i16 @llvm.vector.reduce.umax.v8i16(<8 x i16>) #0413declare i16 @llvm.vector.reduce.umax.v16i16(<16 x i16>) #0414 415;;416;; Vectors of type i32417;;418define dso_local i32 @v2i32(<2 x i32> %a) local_unnamed_addr #0 {419; PWR9LE-LABEL: v2i32:420; PWR9LE: # %bb.0: # %entry421; PWR9LE-NEXT: xxspltw v3, v2, 2422; PWR9LE-NEXT: li r3, 0423; PWR9LE-NEXT: vmaxuw v2, v2, v3424; PWR9LE-NEXT: vextuwrx r3, r3, v2425; PWR9LE-NEXT: blr426;427; PWR9BE-LABEL: v2i32:428; PWR9BE: # %bb.0: # %entry429; PWR9BE-NEXT: xxspltw v3, v2, 1430; PWR9BE-NEXT: li r3, 0431; PWR9BE-NEXT: vmaxuw v2, v2, v3432; PWR9BE-NEXT: vextuwlx r3, r3, v2433; PWR9BE-NEXT: blr434;435; PWR10LE-LABEL: v2i32:436; PWR10LE: # %bb.0: # %entry437; PWR10LE-NEXT: xxspltw v3, v2, 2438; PWR10LE-NEXT: li r3, 0439; PWR10LE-NEXT: vmaxuw v2, v2, v3440; PWR10LE-NEXT: vextuwrx r3, r3, v2441; PWR10LE-NEXT: blr442;443; PWR10BE-LABEL: v2i32:444; PWR10BE: # %bb.0: # %entry445; PWR10BE-NEXT: xxspltw v3, v2, 1446; PWR10BE-NEXT: li r3, 0447; PWR10BE-NEXT: vmaxuw v2, v2, v3448; PWR10BE-NEXT: vextuwlx r3, r3, v2449; PWR10BE-NEXT: blr450entry:451 %0 = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> %a)452 ret i32 %0453}454 455define dso_local i32 @v4i32(<4 x i32> %a) local_unnamed_addr #0 {456; PWR9LE-LABEL: v4i32:457; PWR9LE: # %bb.0: # %entry458; PWR9LE-NEXT: xxswapd v3, v2459; PWR9LE-NEXT: li r3, 0460; PWR9LE-NEXT: vmaxuw v2, v2, v3461; PWR9LE-NEXT: xxspltw v3, v2, 2462; PWR9LE-NEXT: vmaxuw v2, v2, v3463; PWR9LE-NEXT: vextuwrx r3, r3, v2464; PWR9LE-NEXT: blr465;466; PWR9BE-LABEL: v4i32:467; PWR9BE: # %bb.0: # %entry468; PWR9BE-NEXT: xxswapd v3, v2469; PWR9BE-NEXT: li r3, 0470; PWR9BE-NEXT: vmaxuw v2, v2, v3471; PWR9BE-NEXT: xxspltw v3, v2, 1472; PWR9BE-NEXT: vmaxuw v2, v2, v3473; PWR9BE-NEXT: vextuwlx r3, r3, v2474; PWR9BE-NEXT: blr475;476; PWR10LE-LABEL: v4i32:477; PWR10LE: # %bb.0: # %entry478; PWR10LE-NEXT: xxswapd v3, v2479; PWR10LE-NEXT: li r3, 0480; PWR10LE-NEXT: vmaxuw v2, v2, v3481; PWR10LE-NEXT: xxspltw v3, v2, 2482; PWR10LE-NEXT: vmaxuw v2, v2, v3483; PWR10LE-NEXT: vextuwrx r3, r3, v2484; PWR10LE-NEXT: blr485;486; PWR10BE-LABEL: v4i32:487; PWR10BE: # %bb.0: # %entry488; PWR10BE-NEXT: xxswapd v3, v2489; PWR10BE-NEXT: li r3, 0490; PWR10BE-NEXT: vmaxuw v2, v2, v3491; PWR10BE-NEXT: xxspltw v3, v2, 1492; PWR10BE-NEXT: vmaxuw v2, v2, v3493; PWR10BE-NEXT: vextuwlx r3, r3, v2494; PWR10BE-NEXT: blr495entry:496 %0 = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %a)497 ret i32 %0498}499 500define dso_local i32 @v8i32(<8 x i32> %a) local_unnamed_addr #0 {501; PWR9LE-LABEL: v8i32:502; PWR9LE: # %bb.0: # %entry503; PWR9LE-NEXT: vmaxuw v2, v2, v3504; PWR9LE-NEXT: li r3, 0505; PWR9LE-NEXT: xxswapd v3, v2506; PWR9LE-NEXT: vmaxuw v2, v2, v3507; PWR9LE-NEXT: xxspltw v3, v2, 2508; PWR9LE-NEXT: vmaxuw v2, v2, v3509; PWR9LE-NEXT: vextuwrx r3, r3, v2510; PWR9LE-NEXT: blr511;512; PWR9BE-LABEL: v8i32:513; PWR9BE: # %bb.0: # %entry514; PWR9BE-NEXT: vmaxuw v2, v2, v3515; PWR9BE-NEXT: li r3, 0516; PWR9BE-NEXT: xxswapd v3, v2517; PWR9BE-NEXT: vmaxuw v2, v2, v3518; PWR9BE-NEXT: xxspltw v3, v2, 1519; PWR9BE-NEXT: vmaxuw v2, v2, v3520; PWR9BE-NEXT: vextuwlx r3, r3, v2521; PWR9BE-NEXT: blr522;523; PWR10LE-LABEL: v8i32:524; PWR10LE: # %bb.0: # %entry525; PWR10LE-NEXT: vmaxuw v2, v2, v3526; PWR10LE-NEXT: li r3, 0527; PWR10LE-NEXT: xxswapd v3, v2528; PWR10LE-NEXT: vmaxuw v2, v2, v3529; PWR10LE-NEXT: xxspltw v3, v2, 2530; PWR10LE-NEXT: vmaxuw v2, v2, v3531; PWR10LE-NEXT: vextuwrx r3, r3, v2532; PWR10LE-NEXT: blr533;534; PWR10BE-LABEL: v8i32:535; PWR10BE: # %bb.0: # %entry536; PWR10BE-NEXT: vmaxuw v2, v2, v3537; PWR10BE-NEXT: li r3, 0538; PWR10BE-NEXT: xxswapd v3, v2539; PWR10BE-NEXT: vmaxuw v2, v2, v3540; PWR10BE-NEXT: xxspltw v3, v2, 1541; PWR10BE-NEXT: vmaxuw v2, v2, v3542; PWR10BE-NEXT: vextuwlx r3, r3, v2543; PWR10BE-NEXT: blr544entry:545 %0 = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> %a)546 ret i32 %0547}548 549define dso_local i32 @v16i32(<16 x i32> %a) local_unnamed_addr #0 {550; PWR9LE-LABEL: v16i32:551; PWR9LE: # %bb.0: # %entry552; PWR9LE-NEXT: vmaxuw v3, v3, v5553; PWR9LE-NEXT: vmaxuw v2, v2, v4554; PWR9LE-NEXT: li r3, 0555; PWR9LE-NEXT: vmaxuw v2, v2, v3556; PWR9LE-NEXT: xxswapd v3, v2557; PWR9LE-NEXT: vmaxuw v2, v2, v3558; PWR9LE-NEXT: xxspltw v3, v2, 2559; PWR9LE-NEXT: vmaxuw v2, v2, v3560; PWR9LE-NEXT: vextuwrx r3, r3, v2561; PWR9LE-NEXT: blr562;563; PWR9BE-LABEL: v16i32:564; PWR9BE: # %bb.0: # %entry565; PWR9BE-NEXT: vmaxuw v3, v3, v5566; PWR9BE-NEXT: vmaxuw v2, v2, v4567; PWR9BE-NEXT: li r3, 0568; PWR9BE-NEXT: vmaxuw v2, v2, v3569; PWR9BE-NEXT: xxswapd v3, v2570; PWR9BE-NEXT: vmaxuw v2, v2, v3571; PWR9BE-NEXT: xxspltw v3, v2, 1572; PWR9BE-NEXT: vmaxuw v2, v2, v3573; PWR9BE-NEXT: vextuwlx r3, r3, v2574; PWR9BE-NEXT: blr575;576; PWR10LE-LABEL: v16i32:577; PWR10LE: # %bb.0: # %entry578; PWR10LE-NEXT: vmaxuw v3, v3, v5579; PWR10LE-NEXT: vmaxuw v2, v2, v4580; PWR10LE-NEXT: li r3, 0581; PWR10LE-NEXT: vmaxuw v2, v2, v3582; PWR10LE-NEXT: xxswapd v3, v2583; PWR10LE-NEXT: vmaxuw v2, v2, v3584; PWR10LE-NEXT: xxspltw v3, v2, 2585; PWR10LE-NEXT: vmaxuw v2, v2, v3586; PWR10LE-NEXT: vextuwrx r3, r3, v2587; PWR10LE-NEXT: blr588;589; PWR10BE-LABEL: v16i32:590; PWR10BE: # %bb.0: # %entry591; PWR10BE-NEXT: vmaxuw v3, v3, v5592; PWR10BE-NEXT: vmaxuw v2, v2, v4593; PWR10BE-NEXT: li r3, 0594; PWR10BE-NEXT: vmaxuw v2, v2, v3595; PWR10BE-NEXT: xxswapd v3, v2596; PWR10BE-NEXT: vmaxuw v2, v2, v3597; PWR10BE-NEXT: xxspltw v3, v2, 1598; PWR10BE-NEXT: vmaxuw v2, v2, v3599; PWR10BE-NEXT: vextuwlx r3, r3, v2600; PWR10BE-NEXT: blr601entry:602 %0 = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> %a)603 ret i32 %0604}605 606declare i32 @llvm.vector.reduce.umax.v2i32(<2 x i32>) #0607declare i32 @llvm.vector.reduce.umax.v4i32(<4 x i32>) #0608declare i32 @llvm.vector.reduce.umax.v8i32(<8 x i32>) #0609declare i32 @llvm.vector.reduce.umax.v16i32(<16 x i32>) #0610 611;;612;; Vectors of type i64613;;614define dso_local i64 @v2i64(<2 x i64> %a) local_unnamed_addr #0 {615; PWR9LE-LABEL: v2i64:616; PWR9LE: # %bb.0: # %entry617; PWR9LE-NEXT: xxswapd v3, v2618; PWR9LE-NEXT: vmaxud v2, v2, v3619; PWR9LE-NEXT: mfvsrld r3, v2620; PWR9LE-NEXT: blr621;622; PWR9BE-LABEL: v2i64:623; PWR9BE: # %bb.0: # %entry624; PWR9BE-NEXT: xxswapd v3, v2625; PWR9BE-NEXT: vmaxud v2, v2, v3626; PWR9BE-NEXT: mfvsrd r3, v2627; PWR9BE-NEXT: blr628;629; PWR10LE-LABEL: v2i64:630; PWR10LE: # %bb.0: # %entry631; PWR10LE-NEXT: xxswapd v3, v2632; PWR10LE-NEXT: vmaxud v2, v2, v3633; PWR10LE-NEXT: mfvsrld r3, v2634; PWR10LE-NEXT: blr635;636; PWR10BE-LABEL: v2i64:637; PWR10BE: # %bb.0: # %entry638; PWR10BE-NEXT: xxswapd v3, v2639; PWR10BE-NEXT: vmaxud v2, v2, v3640; PWR10BE-NEXT: mfvsrd r3, v2641; PWR10BE-NEXT: blr642entry:643 %0 = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> %a)644 ret i64 %0645}646 647define dso_local i64 @v4i64(<4 x i64> %a) local_unnamed_addr #0 {648; PWR9LE-LABEL: v4i64:649; PWR9LE: # %bb.0: # %entry650; PWR9LE-NEXT: vmaxud v2, v2, v3651; PWR9LE-NEXT: xxswapd v3, v2652; PWR9LE-NEXT: vmaxud v2, v2, v3653; PWR9LE-NEXT: mfvsrld r3, v2654; PWR9LE-NEXT: blr655;656; PWR9BE-LABEL: v4i64:657; PWR9BE: # %bb.0: # %entry658; PWR9BE-NEXT: vmaxud v2, v2, v3659; PWR9BE-NEXT: xxswapd v3, v2660; PWR9BE-NEXT: vmaxud v2, v2, v3661; PWR9BE-NEXT: mfvsrd r3, v2662; PWR9BE-NEXT: blr663;664; PWR10LE-LABEL: v4i64:665; PWR10LE: # %bb.0: # %entry666; PWR10LE-NEXT: vmaxud v2, v2, v3667; PWR10LE-NEXT: xxswapd v3, v2668; PWR10LE-NEXT: vmaxud v2, v2, v3669; PWR10LE-NEXT: mfvsrld r3, v2670; PWR10LE-NEXT: blr671;672; PWR10BE-LABEL: v4i64:673; PWR10BE: # %bb.0: # %entry674; PWR10BE-NEXT: vmaxud v2, v2, v3675; PWR10BE-NEXT: xxswapd v3, v2676; PWR10BE-NEXT: vmaxud v2, v2, v3677; PWR10BE-NEXT: mfvsrd r3, v2678; PWR10BE-NEXT: blr679entry:680 %0 = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> %a)681 ret i64 %0682}683 684define dso_local i64 @v8i64(<8 x i64> %a) local_unnamed_addr #0 {685; PWR9LE-LABEL: v8i64:686; PWR9LE: # %bb.0: # %entry687; PWR9LE-NEXT: vmaxud v2, v2, v4688; PWR9LE-NEXT: vmaxud v3, v3, v5689; PWR9LE-NEXT: vmaxud v2, v2, v3690; PWR9LE-NEXT: xxswapd v3, v2691; PWR9LE-NEXT: vmaxud v2, v2, v3692; PWR9LE-NEXT: mfvsrld r3, v2693; PWR9LE-NEXT: blr694;695; PWR9BE-LABEL: v8i64:696; PWR9BE: # %bb.0: # %entry697; PWR9BE-NEXT: vmaxud v2, v2, v4698; PWR9BE-NEXT: vmaxud v3, v3, v5699; PWR9BE-NEXT: vmaxud v2, v2, v3700; PWR9BE-NEXT: xxswapd v3, v2701; PWR9BE-NEXT: vmaxud v2, v2, v3702; PWR9BE-NEXT: mfvsrd r3, v2703; PWR9BE-NEXT: blr704;705; PWR10LE-LABEL: v8i64:706; PWR10LE: # %bb.0: # %entry707; PWR10LE-NEXT: vmaxud v2, v2, v4708; PWR10LE-NEXT: vmaxud v3, v3, v5709; PWR10LE-NEXT: vmaxud v2, v2, v3710; PWR10LE-NEXT: xxswapd v3, v2711; PWR10LE-NEXT: vmaxud v2, v2, v3712; PWR10LE-NEXT: mfvsrld r3, v2713; PWR10LE-NEXT: blr714;715; PWR10BE-LABEL: v8i64:716; PWR10BE: # %bb.0: # %entry717; PWR10BE-NEXT: vmaxud v2, v2, v4718; PWR10BE-NEXT: vmaxud v3, v3, v5719; PWR10BE-NEXT: vmaxud v2, v2, v3720; PWR10BE-NEXT: xxswapd v3, v2721; PWR10BE-NEXT: vmaxud v2, v2, v3722; PWR10BE-NEXT: mfvsrd r3, v2723; PWR10BE-NEXT: blr724entry:725 %0 = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> %a)726 ret i64 %0727}728 729define dso_local i64 @v16i64(<16 x i64> %a) local_unnamed_addr #0 {730; PWR9LE-LABEL: v16i64:731; PWR9LE: # %bb.0: # %entry732; PWR9LE-NEXT: vmaxud v3, v3, v7733; PWR9LE-NEXT: vmaxud v5, v5, v9734; PWR9LE-NEXT: vmaxud v2, v2, v6735; PWR9LE-NEXT: vmaxud v4, v4, v8736; PWR9LE-NEXT: vmaxud v2, v2, v4737; PWR9LE-NEXT: vmaxud v3, v3, v5738; PWR9LE-NEXT: vmaxud v2, v2, v3739; PWR9LE-NEXT: xxswapd v3, v2740; PWR9LE-NEXT: vmaxud v2, v2, v3741; PWR9LE-NEXT: mfvsrld r3, v2742; PWR9LE-NEXT: blr743;744; PWR9BE-LABEL: v16i64:745; PWR9BE: # %bb.0: # %entry746; PWR9BE-NEXT: vmaxud v3, v3, v7747; PWR9BE-NEXT: vmaxud v5, v5, v9748; PWR9BE-NEXT: vmaxud v2, v2, v6749; PWR9BE-NEXT: vmaxud v4, v4, v8750; PWR9BE-NEXT: vmaxud v2, v2, v4751; PWR9BE-NEXT: vmaxud v3, v3, v5752; PWR9BE-NEXT: vmaxud v2, v2, v3753; PWR9BE-NEXT: xxswapd v3, v2754; PWR9BE-NEXT: vmaxud v2, v2, v3755; PWR9BE-NEXT: mfvsrd r3, v2756; PWR9BE-NEXT: blr757;758; PWR10LE-LABEL: v16i64:759; PWR10LE: # %bb.0: # %entry760; PWR10LE-NEXT: vmaxud v3, v3, v7761; PWR10LE-NEXT: vmaxud v5, v5, v9762; PWR10LE-NEXT: vmaxud v2, v2, v6763; PWR10LE-NEXT: vmaxud v4, v4, v8764; PWR10LE-NEXT: vmaxud v2, v2, v4765; PWR10LE-NEXT: vmaxud v3, v3, v5766; PWR10LE-NEXT: vmaxud v2, v2, v3767; PWR10LE-NEXT: xxswapd v3, v2768; PWR10LE-NEXT: vmaxud v2, v2, v3769; PWR10LE-NEXT: mfvsrld r3, v2770; PWR10LE-NEXT: blr771;772; PWR10BE-LABEL: v16i64:773; PWR10BE: # %bb.0: # %entry774; PWR10BE-NEXT: vmaxud v3, v3, v7775; PWR10BE-NEXT: vmaxud v5, v5, v9776; PWR10BE-NEXT: vmaxud v2, v2, v6777; PWR10BE-NEXT: vmaxud v4, v4, v8778; PWR10BE-NEXT: vmaxud v2, v2, v4779; PWR10BE-NEXT: vmaxud v3, v3, v5780; PWR10BE-NEXT: vmaxud v2, v2, v3781; PWR10BE-NEXT: xxswapd v3, v2782; PWR10BE-NEXT: vmaxud v2, v2, v3783; PWR10BE-NEXT: mfvsrd r3, v2784; PWR10BE-NEXT: blr785entry:786 %0 = call i64 @llvm.vector.reduce.umax.v16i64(<16 x i64> %a)787 ret i64 %0788}789 790declare i64 @llvm.vector.reduce.umax.v2i64(<2 x i64>) #0791declare i64 @llvm.vector.reduce.umax.v4i64(<4 x i64>) #0792declare i64 @llvm.vector.reduce.umax.v8i64(<8 x i64>) #0793declare i64 @llvm.vector.reduce.umax.v16i64(<16 x i64>) #0794 795 796attributes #0 = { nounwind }797