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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \3; RUN: -mcpu=pwr9 -mtriple=powerpc64le < %s | FileCheck %s --check-prefix=PWR9LE4; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \5; RUN: -mcpu=pwr9 -mtriple=powerpc64 < %s | FileCheck %s --check-prefix=PWR9BE6; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \7; RUN: -mcpu=pwr10 -mtriple=powerpc64le < %s | FileCheck %s --check-prefix=PWR10LE8; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \9; RUN: -mcpu=pwr10 -mtriple=powerpc64 < %s | FileCheck %s --check-prefix=PWR10BE10 11;;12;; Vectors of type i3213;;14define dso_local i32 @v2i32(<2 x i32> %a) local_unnamed_addr #0 {15; PWR9LE-LABEL: v2i32:16; PWR9LE: # %bb.0: # %entry17; PWR9LE-NEXT: xxspltw vs0, v2, 218; PWR9LE-NEXT: li r3, 019; PWR9LE-NEXT: xxlxor v2, v2, vs020; PWR9LE-NEXT: vextuwrx r3, r3, v221; PWR9LE-NEXT: blr22;23; PWR9BE-LABEL: v2i32:24; PWR9BE: # %bb.0: # %entry25; PWR9BE-NEXT: xxspltw vs0, v2, 126; PWR9BE-NEXT: li r3, 027; PWR9BE-NEXT: xxlxor v2, v2, vs028; PWR9BE-NEXT: vextuwlx r3, r3, v229; PWR9BE-NEXT: blr30;31; PWR10LE-LABEL: v2i32:32; PWR10LE: # %bb.0: # %entry33; PWR10LE-NEXT: xxspltw vs0, v2, 234; PWR10LE-NEXT: li r3, 035; PWR10LE-NEXT: xxlxor v2, v2, vs036; PWR10LE-NEXT: vextuwrx r3, r3, v237; PWR10LE-NEXT: blr38;39; PWR10BE-LABEL: v2i32:40; PWR10BE: # %bb.0: # %entry41; PWR10BE-NEXT: xxspltw vs0, v2, 142; PWR10BE-NEXT: li r3, 043; PWR10BE-NEXT: xxlxor v2, v2, vs044; PWR10BE-NEXT: vextuwlx r3, r3, v245; PWR10BE-NEXT: blr46entry:47 %0 = call i32 @llvm.vector.reduce.xor.v2i32(<2 x i32> %a)48 ret i32 %049}50 51define dso_local i32 @v4i32(<4 x i32> %a) local_unnamed_addr #0 {52; PWR9LE-LABEL: v4i32:53; PWR9LE: # %bb.0: # %entry54; PWR9LE-NEXT: xxswapd v3, v255; PWR9LE-NEXT: li r3, 056; PWR9LE-NEXT: xxlxor vs0, v2, v357; PWR9LE-NEXT: xxspltw vs1, vs0, 258; PWR9LE-NEXT: xxlxor v2, vs0, vs159; PWR9LE-NEXT: vextuwrx r3, r3, v260; PWR9LE-NEXT: blr61;62; PWR9BE-LABEL: v4i32:63; PWR9BE: # %bb.0: # %entry64; PWR9BE-NEXT: xxswapd v3, v265; PWR9BE-NEXT: li r3, 066; PWR9BE-NEXT: xxlxor vs0, v2, v367; PWR9BE-NEXT: xxspltw vs1, vs0, 168; PWR9BE-NEXT: xxlxor v2, vs0, vs169; PWR9BE-NEXT: vextuwlx r3, r3, v270; PWR9BE-NEXT: blr71;72; PWR10LE-LABEL: v4i32:73; PWR10LE: # %bb.0: # %entry74; PWR10LE-NEXT: xxswapd v3, v275; PWR10LE-NEXT: li r3, 076; PWR10LE-NEXT: xxlxor vs0, v2, v377; PWR10LE-NEXT: xxspltw vs0, vs0, 278; PWR10LE-NEXT: xxeval v2, v2, v3, vs0, 10579; PWR10LE-NEXT: vextuwrx r3, r3, v280; PWR10LE-NEXT: blr81;82; PWR10BE-LABEL: v4i32:83; PWR10BE: # %bb.0: # %entry84; PWR10BE-NEXT: xxswapd v3, v285; PWR10BE-NEXT: li r3, 086; PWR10BE-NEXT: xxlxor vs0, v2, v387; PWR10BE-NEXT: xxspltw vs0, vs0, 188; PWR10BE-NEXT: xxeval v2, v2, v3, vs0, 10589; PWR10BE-NEXT: vextuwlx r3, r3, v290; PWR10BE-NEXT: blr91entry:92 %0 = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %a)93 ret i32 %094}95 96define dso_local i32 @v8i32(<8 x i32> %a) local_unnamed_addr #0 {97; PWR9LE-LABEL: v8i32:98; PWR9LE: # %bb.0: # %entry99; PWR9LE-NEXT: xxlxor vs0, v2, v3100; PWR9LE-NEXT: li r3, 0101; PWR9LE-NEXT: xxswapd v2, vs0102; PWR9LE-NEXT: xxlxor vs0, vs0, v2103; PWR9LE-NEXT: xxspltw vs1, vs0, 2104; PWR9LE-NEXT: xxlxor v2, vs0, vs1105; PWR9LE-NEXT: vextuwrx r3, r3, v2106; PWR9LE-NEXT: blr107;108; PWR9BE-LABEL: v8i32:109; PWR9BE: # %bb.0: # %entry110; PWR9BE-NEXT: xxlxor vs0, v2, v3111; PWR9BE-NEXT: li r3, 0112; PWR9BE-NEXT: xxswapd v2, vs0113; PWR9BE-NEXT: xxlxor vs0, vs0, v2114; PWR9BE-NEXT: xxspltw vs1, vs0, 1115; PWR9BE-NEXT: xxlxor v2, vs0, vs1116; PWR9BE-NEXT: vextuwlx r3, r3, v2117; PWR9BE-NEXT: blr118;119; PWR10LE-LABEL: v8i32:120; PWR10LE: # %bb.0: # %entry121; PWR10LE-NEXT: xxlxor vs0, v2, v3122; PWR10LE-NEXT: li r3, 0123; PWR10LE-NEXT: xxswapd v4, vs0124; PWR10LE-NEXT: xxeval vs1, v2, v3, v4, 105125; PWR10LE-NEXT: xxspltw vs1, vs1, 2126; PWR10LE-NEXT: xxeval v2, vs0, v4, vs1, 105127; PWR10LE-NEXT: vextuwrx r3, r3, v2128; PWR10LE-NEXT: blr129;130; PWR10BE-LABEL: v8i32:131; PWR10BE: # %bb.0: # %entry132; PWR10BE-NEXT: xxlxor vs0, v2, v3133; PWR10BE-NEXT: li r3, 0134; PWR10BE-NEXT: xxswapd v4, vs0135; PWR10BE-NEXT: xxeval vs1, v2, v3, v4, 105136; PWR10BE-NEXT: xxspltw vs1, vs1, 1137; PWR10BE-NEXT: xxeval v2, vs0, v4, vs1, 105138; PWR10BE-NEXT: vextuwlx r3, r3, v2139; PWR10BE-NEXT: blr140entry:141 %0 = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> %a)142 ret i32 %0143}144 145define dso_local i32 @v16i32(<16 x i32> %a) local_unnamed_addr #0 {146; PWR9LE-LABEL: v16i32:147; PWR9LE: # %bb.0: # %entry148; PWR9LE-NEXT: xxlxor vs0, v3, v5149; PWR9LE-NEXT: xxlxor vs1, v2, v4150; PWR9LE-NEXT: li r3, 0151; PWR9LE-NEXT: xxlxor vs0, vs1, vs0152; PWR9LE-NEXT: xxswapd v2, vs0153; PWR9LE-NEXT: xxlxor vs0, vs0, v2154; PWR9LE-NEXT: xxspltw vs1, vs0, 2155; PWR9LE-NEXT: xxlxor v2, vs0, vs1156; PWR9LE-NEXT: vextuwrx r3, r3, v2157; PWR9LE-NEXT: blr158;159; PWR9BE-LABEL: v16i32:160; PWR9BE: # %bb.0: # %entry161; PWR9BE-NEXT: xxlxor vs0, v3, v5162; PWR9BE-NEXT: xxlxor vs1, v2, v4163; PWR9BE-NEXT: li r3, 0164; PWR9BE-NEXT: xxlxor vs0, vs1, vs0165; PWR9BE-NEXT: xxswapd v2, vs0166; PWR9BE-NEXT: xxlxor vs0, vs0, v2167; PWR9BE-NEXT: xxspltw vs1, vs0, 1168; PWR9BE-NEXT: xxlxor v2, vs0, vs1169; PWR9BE-NEXT: vextuwlx r3, r3, v2170; PWR9BE-NEXT: blr171;172; PWR10LE-LABEL: v16i32:173; PWR10LE: # %bb.0: # %entry174; PWR10LE-NEXT: xxlxor vs1, v2, v4175; PWR10LE-NEXT: xxlxor vs0, v3, v5176; PWR10LE-NEXT: li r3, 0177; PWR10LE-NEXT: xxeval vs2, vs1, v3, v5, 105178; PWR10LE-NEXT: xxswapd v2, vs2179; PWR10LE-NEXT: xxeval vs0, vs1, vs0, v2, 105180; PWR10LE-NEXT: xxspltw vs0, vs0, 2181; PWR10LE-NEXT: xxeval v2, vs2, v2, vs0, 105182; PWR10LE-NEXT: vextuwrx r3, r3, v2183; PWR10LE-NEXT: blr184;185; PWR10BE-LABEL: v16i32:186; PWR10BE: # %bb.0: # %entry187; PWR10BE-NEXT: xxlxor vs1, v2, v4188; PWR10BE-NEXT: xxlxor vs0, v3, v5189; PWR10BE-NEXT: li r3, 0190; PWR10BE-NEXT: xxeval vs2, vs1, v3, v5, 105191; PWR10BE-NEXT: xxswapd v2, vs2192; PWR10BE-NEXT: xxeval vs0, vs1, vs0, v2, 105193; PWR10BE-NEXT: xxspltw vs0, vs0, 1194; PWR10BE-NEXT: xxeval v2, vs2, v2, vs0, 105195; PWR10BE-NEXT: vextuwlx r3, r3, v2196; PWR10BE-NEXT: blr197entry:198 %0 = call i32 @llvm.vector.reduce.xor.v16i32(<16 x i32> %a)199 ret i32 %0200}201 202declare i32 @llvm.vector.reduce.xor.v2i32(<2 x i32>) #0203declare i32 @llvm.vector.reduce.xor.v4i32(<4 x i32>) #0204declare i32 @llvm.vector.reduce.xor.v8i32(<8 x i32>) #0205declare i32 @llvm.vector.reduce.xor.v16i32(<16 x i32>) #0206 207;;208;; Vectors of type i64209;;210define dso_local i64 @v2i64(<2 x i64> %a) local_unnamed_addr #0 {211; PWR9LE-LABEL: v2i64:212; PWR9LE: # %bb.0: # %entry213; PWR9LE-NEXT: xxswapd v3, v2214; PWR9LE-NEXT: xxlxor vs0, v2, v3215; PWR9LE-NEXT: mfvsrld r3, vs0216; PWR9LE-NEXT: blr217;218; PWR9BE-LABEL: v2i64:219; PWR9BE: # %bb.0: # %entry220; PWR9BE-NEXT: xxswapd v3, v2221; PWR9BE-NEXT: xxlxor vs0, v2, v3222; PWR9BE-NEXT: mffprd r3, f0223; PWR9BE-NEXT: blr224;225; PWR10LE-LABEL: v2i64:226; PWR10LE: # %bb.0: # %entry227; PWR10LE-NEXT: xxswapd v3, v2228; PWR10LE-NEXT: xxlxor vs0, v2, v3229; PWR10LE-NEXT: mfvsrld r3, vs0230; PWR10LE-NEXT: blr231;232; PWR10BE-LABEL: v2i64:233; PWR10BE: # %bb.0: # %entry234; PWR10BE-NEXT: xxswapd v3, v2235; PWR10BE-NEXT: xxlxor vs0, v2, v3236; PWR10BE-NEXT: mffprd r3, f0237; PWR10BE-NEXT: blr238entry:239 %0 = call i64 @llvm.vector.reduce.xor.v2i64(<2 x i64> %a)240 ret i64 %0241}242 243define dso_local i64 @v4i64(<4 x i64> %a) local_unnamed_addr #0 {244; PWR9LE-LABEL: v4i64:245; PWR9LE: # %bb.0: # %entry246; PWR9LE-NEXT: xxlxor vs0, v2, v3247; PWR9LE-NEXT: xxswapd v2, vs0248; PWR9LE-NEXT: xxlxor vs0, vs0, v2249; PWR9LE-NEXT: mfvsrld r3, vs0250; PWR9LE-NEXT: blr251;252; PWR9BE-LABEL: v4i64:253; PWR9BE: # %bb.0: # %entry254; PWR9BE-NEXT: xxlxor vs0, v2, v3255; PWR9BE-NEXT: xxswapd v2, vs0256; PWR9BE-NEXT: xxlxor vs0, vs0, v2257; PWR9BE-NEXT: mffprd r3, f0258; PWR9BE-NEXT: blr259;260; PWR10LE-LABEL: v4i64:261; PWR10LE: # %bb.0: # %entry262; PWR10LE-NEXT: xxlxor vs0, v2, v3263; PWR10LE-NEXT: xxswapd v4, vs0264; PWR10LE-NEXT: xxeval vs0, v2, v3, v4, 105265; PWR10LE-NEXT: mfvsrld r3, vs0266; PWR10LE-NEXT: blr267;268; PWR10BE-LABEL: v4i64:269; PWR10BE: # %bb.0: # %entry270; PWR10BE-NEXT: xxlxor vs0, v2, v3271; PWR10BE-NEXT: xxswapd v4, vs0272; PWR10BE-NEXT: xxeval vs0, v2, v3, v4, 105273; PWR10BE-NEXT: mffprd r3, f0274; PWR10BE-NEXT: blr275entry:276 %0 = call i64 @llvm.vector.reduce.xor.v4i64(<4 x i64> %a)277 ret i64 %0278}279 280define dso_local i64 @v8i64(<8 x i64> %a) local_unnamed_addr #0 {281; PWR9LE-LABEL: v8i64:282; PWR9LE: # %bb.0: # %entry283; PWR9LE-NEXT: xxlxor vs0, v3, v5284; PWR9LE-NEXT: xxlxor vs1, v2, v4285; PWR9LE-NEXT: xxlxor vs0, vs1, vs0286; PWR9LE-NEXT: xxswapd v2, vs0287; PWR9LE-NEXT: xxlxor vs0, vs0, v2288; PWR9LE-NEXT: mfvsrld r3, vs0289; PWR9LE-NEXT: blr290;291; PWR9BE-LABEL: v8i64:292; PWR9BE: # %bb.0: # %entry293; PWR9BE-NEXT: xxlxor vs0, v3, v5294; PWR9BE-NEXT: xxlxor vs1, v2, v4295; PWR9BE-NEXT: xxlxor vs0, vs1, vs0296; PWR9BE-NEXT: xxswapd v2, vs0297; PWR9BE-NEXT: xxlxor vs0, vs0, v2298; PWR9BE-NEXT: mffprd r3, f0299; PWR9BE-NEXT: blr300;301; PWR10LE-LABEL: v8i64:302; PWR10LE: # %bb.0: # %entry303; PWR10LE-NEXT: xxlxor vs1, v2, v4304; PWR10LE-NEXT: xxlxor vs0, v3, v5305; PWR10LE-NEXT: xxeval vs2, vs1, v3, v5, 105306; PWR10LE-NEXT: xxswapd v2, vs2307; PWR10LE-NEXT: xxeval vs0, vs1, vs0, v2, 105308; PWR10LE-NEXT: mfvsrld r3, vs0309; PWR10LE-NEXT: blr310;311; PWR10BE-LABEL: v8i64:312; PWR10BE: # %bb.0: # %entry313; PWR10BE-NEXT: xxlxor vs1, v2, v4314; PWR10BE-NEXT: xxlxor vs0, v3, v5315; PWR10BE-NEXT: xxeval vs2, vs1, v3, v5, 105316; PWR10BE-NEXT: xxswapd v2, vs2317; PWR10BE-NEXT: xxeval vs0, vs1, vs0, v2, 105318; PWR10BE-NEXT: mffprd r3, f0319; PWR10BE-NEXT: blr320entry:321 %0 = call i64 @llvm.vector.reduce.xor.v8i64(<8 x i64> %a)322 ret i64 %0323}324 325define dso_local i64 @v16i64(<16 x i64> %a) local_unnamed_addr #0 {326; PWR9LE-LABEL: v16i64:327; PWR9LE: # %bb.0: # %entry328; PWR9LE-NEXT: xxlxor vs0, v4, v8329; PWR9LE-NEXT: xxlxor vs1, v2, v6330; PWR9LE-NEXT: xxlxor vs2, v5, v9331; PWR9LE-NEXT: xxlxor vs3, v3, v7332; PWR9LE-NEXT: xxlxor vs2, vs3, vs2333; PWR9LE-NEXT: xxlxor vs0, vs1, vs0334; PWR9LE-NEXT: xxlxor vs0, vs0, vs2335; PWR9LE-NEXT: xxswapd v2, vs0336; PWR9LE-NEXT: xxlxor vs0, vs0, v2337; PWR9LE-NEXT: mfvsrld r3, vs0338; PWR9LE-NEXT: blr339;340; PWR9BE-LABEL: v16i64:341; PWR9BE: # %bb.0: # %entry342; PWR9BE-NEXT: xxlxor vs0, v4, v8343; PWR9BE-NEXT: xxlxor vs1, v2, v6344; PWR9BE-NEXT: xxlxor vs2, v5, v9345; PWR9BE-NEXT: xxlxor vs3, v3, v7346; PWR9BE-NEXT: xxlxor vs2, vs3, vs2347; PWR9BE-NEXT: xxlxor vs0, vs1, vs0348; PWR9BE-NEXT: xxlxor vs0, vs0, vs2349; PWR9BE-NEXT: xxswapd v2, vs0350; PWR9BE-NEXT: xxlxor vs0, vs0, v2351; PWR9BE-NEXT: mffprd r3, f0352; PWR9BE-NEXT: blr353;354; PWR10LE-LABEL: v16i64:355; PWR10LE: # %bb.0: # %entry356; PWR10LE-NEXT: xxlxor vs1, v2, v6357; PWR10LE-NEXT: xxlxor vs0, v5, v9358; PWR10LE-NEXT: xxlxor vs2, v3, v7359; PWR10LE-NEXT: xxeval vs1, vs1, v4, v8, 105360; PWR10LE-NEXT: xxeval vs3, vs2, v5, v9, 105361; PWR10LE-NEXT: xxeval vs0, vs1, vs2, vs0, 105362; PWR10LE-NEXT: xxswapd v2, vs0363; PWR10LE-NEXT: xxeval vs0, vs1, vs3, v2, 105364; PWR10LE-NEXT: mfvsrld r3, vs0365; PWR10LE-NEXT: blr366;367; PWR10BE-LABEL: v16i64:368; PWR10BE: # %bb.0: # %entry369; PWR10BE-NEXT: xxlxor vs1, v2, v6370; PWR10BE-NEXT: xxlxor vs0, v5, v9371; PWR10BE-NEXT: xxlxor vs2, v3, v7372; PWR10BE-NEXT: xxeval vs1, vs1, v4, v8, 105373; PWR10BE-NEXT: xxeval vs3, vs2, v5, v9, 105374; PWR10BE-NEXT: xxeval vs0, vs1, vs2, vs0, 105375; PWR10BE-NEXT: xxswapd v2, vs0376; PWR10BE-NEXT: xxeval vs0, vs1, vs3, v2, 105377; PWR10BE-NEXT: mffprd r3, f0378; PWR10BE-NEXT: blr379entry:380 %0 = call i64 @llvm.vector.reduce.xor.v16i64(<16 x i64> %a)381 ret i64 %0382}383 384declare i64 @llvm.vector.reduce.xor.v2i64(<2 x i64>) #0385declare i64 @llvm.vector.reduce.xor.v4i64(<4 x i64>) #0386declare i64 @llvm.vector.reduce.xor.v8i64(<8 x i64>) #0387declare i64 @llvm.vector.reduce.xor.v16i64(<16 x i64>) #0388 389 390attributes #0 = { nounwind }391