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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -O3 -mtriple=powerpc64le-unknown-unknown -ppc-asm-full-reg-names \3; RUN: -verify-machineinstrs -mcpu=pwr8 < %s | \4; RUN: FileCheck --check-prefix=CHECK-P8 %s5; RUN: llc -O3 -mtriple=powerpc64-unknown-unknown -ppc-asm-full-reg-names \6; RUN: -verify-machineinstrs -mcpu=pwr7 < %s | \7; RUN: FileCheck --check-prefix=CHECK-P7 %s8; RUN: llc -O3 -mtriple=powerpc64-unknown-unknown -ppc-asm-full-reg-names \9; RUN: -verify-machineinstrs -mcpu=future < %s | \10; RUN: FileCheck --check-prefix=CHECK-FUTURE %s11 12define <16 x i8> @rotl_v16i8(<16 x i8> %a) {13; CHECK-P8-LABEL: rotl_v16i8:14; CHECK-P8: # %bb.0: # %entry15; CHECK-P8-NEXT: addis r3, r2, .LCPI0_0@toc@ha16; CHECK-P8-NEXT: addi r3, r3, .LCPI0_0@toc@l17; CHECK-P8-NEXT: lxvd2x vs0, 0, r318; CHECK-P8-NEXT: xxswapd vs35, vs019; CHECK-P8-NEXT: vrlb v2, v2, v320; CHECK-P8-NEXT: blr21;22; CHECK-P7-LABEL: rotl_v16i8:23; CHECK-P7: # %bb.0: # %entry24; CHECK-P7-NEXT: addis r3, r2, .LCPI0_0@toc@ha25; CHECK-P7-NEXT: addi r3, r3, .LCPI0_0@toc@l26; CHECK-P7-NEXT: lxvw4x vs35, 0, r327; CHECK-P7-NEXT: vrlb v2, v2, v328; CHECK-P7-NEXT: blr29;30; CHECK-FUTURE-LABEL: rotl_v16i8:31; CHECK-FUTURE: # %bb.0: # %entry32; CHECK-FUTURE-NEXT: addis r3, r2, .LCPI0_0@toc@ha33; CHECK-FUTURE-NEXT: addi r3, r3, .LCPI0_0@toc@l34; CHECK-FUTURE-NEXT: lxv vs35, 0(r3)35; CHECK-FUTURE-NEXT: vrlb v2, v2, v336; CHECK-FUTURE-NEXT: blr37entry:38 %b = shl <16 x i8> %a, <i8 1, i8 1, i8 2, i8 2, i8 3, i8 3, i8 4, i8 4, i8 5, i8 5, i8 6, i8 6, i8 7, i8 7, i8 8, i8 8>39 %c = lshr <16 x i8> %a, <i8 7, i8 7, i8 6, i8 6, i8 5, i8 5, i8 4, i8 4, i8 3, i8 3, i8 2, i8 2, i8 1, i8 1, i8 0, i8 0>40 %d = or <16 x i8> %b, %c41 ret <16 x i8> %d42}43 44define <8 x i16> @rotl_v8i16(<8 x i16> %a) {45; CHECK-P8-LABEL: rotl_v8i16:46; CHECK-P8: # %bb.0: # %entry47; CHECK-P8-NEXT: addis r3, r2, .LCPI1_0@toc@ha48; CHECK-P8-NEXT: addi r3, r3, .LCPI1_0@toc@l49; CHECK-P8-NEXT: lxvd2x vs0, 0, r350; CHECK-P8-NEXT: xxswapd vs35, vs051; CHECK-P8-NEXT: vrlh v2, v2, v352; CHECK-P8-NEXT: blr53;54; CHECK-P7-LABEL: rotl_v8i16:55; CHECK-P7: # %bb.0: # %entry56; CHECK-P7-NEXT: addis r3, r2, .LCPI1_0@toc@ha57; CHECK-P7-NEXT: addi r3, r3, .LCPI1_0@toc@l58; CHECK-P7-NEXT: lxvw4x vs35, 0, r359; CHECK-P7-NEXT: vrlh v2, v2, v360; CHECK-P7-NEXT: blr61;62; CHECK-FUTURE-LABEL: rotl_v8i16:63; CHECK-FUTURE: # %bb.0: # %entry64; CHECK-FUTURE-NEXT: addis r3, r2, .LCPI1_0@toc@ha65; CHECK-FUTURE-NEXT: addi r3, r3, .LCPI1_0@toc@l66; CHECK-FUTURE-NEXT: lxv vs35, 0(r3)67; CHECK-FUTURE-NEXT: vrlh v2, v2, v368; CHECK-FUTURE-NEXT: blr69entry:70 %b = shl <8 x i16> %a, <i16 1, i16 2, i16 3, i16 5, i16 7, i16 11, i16 13, i16 16>71 %c = lshr <8 x i16> %a, <i16 15, i16 14, i16 13, i16 11, i16 9, i16 5, i16 3, i16 0>72 %d = or <8 x i16> %b, %c73 ret <8 x i16> %d74}75 76define <4 x i32> @rotl_v4i32_0(<4 x i32> %a) {77; CHECK-P8-LABEL: rotl_v4i32_0:78; CHECK-P8: # %bb.0: # %entry79; CHECK-P8-NEXT: addis r3, r2, .LCPI2_0@toc@ha80; CHECK-P8-NEXT: addi r3, r3, .LCPI2_0@toc@l81; CHECK-P8-NEXT: lxvd2x vs0, 0, r382; CHECK-P8-NEXT: xxswapd vs35, vs083; CHECK-P8-NEXT: vrlw v2, v2, v384; CHECK-P8-NEXT: blr85;86; CHECK-P7-LABEL: rotl_v4i32_0:87; CHECK-P7: # %bb.0: # %entry88; CHECK-P7-NEXT: addis r3, r2, .LCPI2_0@toc@ha89; CHECK-P7-NEXT: addi r3, r3, .LCPI2_0@toc@l90; CHECK-P7-NEXT: lxvw4x vs35, 0, r391; CHECK-P7-NEXT: vrlw v2, v2, v392; CHECK-P7-NEXT: blr93;94; CHECK-FUTURE-LABEL: rotl_v4i32_0:95; CHECK-FUTURE: # %bb.0: # %entry96; CHECK-FUTURE-NEXT: addis r3, r2, .LCPI2_0@toc@ha97; CHECK-FUTURE-NEXT: addi r3, r3, .LCPI2_0@toc@l98; CHECK-FUTURE-NEXT: lxv vs0, 0(r3)99; CHECK-FUTURE-NEXT: xvrlw vs34, vs34, vs0100; CHECK-FUTURE-NEXT: blr101entry:102 %b = shl <4 x i32> %a, <i32 29, i32 19, i32 17, i32 11>103 %c = lshr <4 x i32> %a, <i32 3, i32 13, i32 15, i32 21>104 %d = or <4 x i32> %b, %c105 ret <4 x i32> %d106}107 108define <4 x i32> @rotl_v4i32_1(<4 x i32> %a) {109; CHECK-P8-LABEL: rotl_v4i32_1:110; CHECK-P8: # %bb.0: # %entry111; CHECK-P8-NEXT: vspltisw v3, -16112; CHECK-P8-NEXT: vspltisw v4, 7113; CHECK-P8-NEXT: vsubuwm v3, v4, v3114; CHECK-P8-NEXT: vrlw v2, v2, v3115; CHECK-P8-NEXT: blr116;117; CHECK-P7-LABEL: rotl_v4i32_1:118; CHECK-P7: # %bb.0: # %entry119; CHECK-P7-NEXT: vspltisw v3, -16120; CHECK-P7-NEXT: vspltisw v4, 7121; CHECK-P7-NEXT: vsubuwm v3, v4, v3122; CHECK-P7-NEXT: vrlw v2, v2, v3123; CHECK-P7-NEXT: blr124;125; CHECK-FUTURE-LABEL: rotl_v4i32_1:126; CHECK-FUTURE: # %bb.0: # %entry127; CHECK-FUTURE-NEXT: xxspltiw vs0, 23128; CHECK-FUTURE-NEXT: xvrlw vs34, vs34, vs0129; CHECK-FUTURE-NEXT: blr130entry:131 %b = shl <4 x i32> %a, <i32 23, i32 23, i32 23, i32 23>132 %c = lshr <4 x i32> %a, <i32 9, i32 9, i32 9, i32 9>133 %d = or <4 x i32> %b, %c134 ret <4 x i32> %d135}136 137define <2 x i64> @rotl_v2i64(<2 x i64> %a) {138; CHECK-P8-LABEL: rotl_v2i64:139; CHECK-P8: # %bb.0: # %entry140; CHECK-P8-NEXT: addis r3, r2, .LCPI4_0@toc@ha141; CHECK-P8-NEXT: addi r3, r3, .LCPI4_0@toc@l142; CHECK-P8-NEXT: lxvd2x vs0, 0, r3143; CHECK-P8-NEXT: xxswapd vs35, vs0144; CHECK-P8-NEXT: vrld v2, v2, v3145; CHECK-P8-NEXT: blr146;147; CHECK-P7-LABEL: rotl_v2i64:148; CHECK-P7: # %bb.0: # %entry149; CHECK-P7-NEXT: addi r3, r1, -32150; CHECK-P7-NEXT: stxvd2x vs34, 0, r3151; CHECK-P7-NEXT: ld r3, -24(r1)152; CHECK-P7-NEXT: rotldi r3, r3, 53153; CHECK-P7-NEXT: std r3, -8(r1)154; CHECK-P7-NEXT: ld r3, -32(r1)155; CHECK-P7-NEXT: rotldi r3, r3, 41156; CHECK-P7-NEXT: std r3, -16(r1)157; CHECK-P7-NEXT: addi r3, r1, -16158; CHECK-P7-NEXT: lxvd2x vs34, 0, r3159; CHECK-P7-NEXT: blr160;161; CHECK-FUTURE-LABEL: rotl_v2i64:162; CHECK-FUTURE: # %bb.0: # %entry163; CHECK-FUTURE-NEXT: addis r3, r2, .LCPI4_0@toc@ha164; CHECK-FUTURE-NEXT: addi r3, r3, .LCPI4_0@toc@l165; CHECK-FUTURE-NEXT: lxv vs35, 0(r3)166; CHECK-FUTURE-NEXT: vrld v2, v2, v3167; CHECK-FUTURE-NEXT: blr168entry:169 %b = shl <2 x i64> %a, <i64 41, i64 53>170 %c = lshr <2 x i64> %a, <i64 23, i64 11>171 %d = or <2 x i64> %b, %c172 ret <2 x i64> %d173}174