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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \3; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s4; RUN: llc -verify-machineinstrs -mtriple=powerpc64-aix-xcoff \5; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s6; RUN: llc -verify-machineinstrs -mtriple=powerpc-aix-xcoff \7; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s8 9define void @test1(<16 x i8> %0) {10; CHECK-LABEL: test1:11; CHECK: # %bb.0: # %entry12; CHECK-NEXT: blr13entry:14 %1 = tail call <4 x i32> @llvm.ppc.altivec.vsum4sbs(<16 x i8> %0, <4 x i32> zeroinitializer)15 ret void16}17 18define void @test2(<8 x i16> %0) {19; CHECK-LABEL: test2:20; CHECK: # %bb.0: # %entry21; CHECK-NEXT: blr22entry:23 %1 = tail call <4 x i32> @llvm.ppc.altivec.vsum4shs(<8 x i16> %0, <4 x i32> zeroinitializer)24 ret void25}26 27define void @test3(<16 x i8> %0) {28; CHECK-LABEL: test3:29; CHECK: # %bb.0: # %entry30; CHECK-NEXT: blr31entry:32 %1 = tail call <4 x i32> @llvm.ppc.altivec.vsum4ubs(<16 x i8> %0, <4 x i32> zeroinitializer)33 ret void34}35 36define void @test4(<16 x i8> %0) {37; CHECK-LABEL: test4:38; CHECK: # %bb.0: # %entry39; CHECK-NEXT: vspltisw v3, 140; CHECK-NEXT: vsum4sbs v2, v2, v341; CHECK-NEXT: blr42entry:43 %1 = tail call <4 x i32> @llvm.ppc.altivec.vsum4sbs(<16 x i8> %0, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)44 ret void45}46 47define void @test5(<8 x i16> %0) {48; CHECK-LABEL: test5:49; CHECK: # %bb.0: # %entry50; CHECK-NEXT: vspltisw v3, 151; CHECK-NEXT: vsum4shs v2, v2, v352; CHECK-NEXT: blr53entry:54 %1 = tail call <4 x i32> @llvm.ppc.altivec.vsum4shs(<8 x i16> %0, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)55 ret void56}57 58define void @test6(<16 x i8> %0) {59; CHECK-LABEL: test6:60; CHECK: # %bb.0: # %entry61; CHECK-NEXT: vspltisw v3, 162; CHECK-NEXT: vsum4ubs v2, v2, v363; CHECK-NEXT: blr64entry:65 %1 = tail call <4 x i32> @llvm.ppc.altivec.vsum4ubs(<16 x i8> %0, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)66 ret void67}68 69define <4 x i32> @test7(<16 x i8> %0) {70; CHECK-LABEL: test7:71; CHECK: # %bb.0: # %entry72; CHECK-NEXT: xxlxor v3, v3, v373; CHECK-NEXT: vsum4sbs v2, v2, v374; CHECK-NEXT: blr75entry:76 %1 = tail call <4 x i32> @llvm.ppc.altivec.vsum4sbs(<16 x i8> %0, <4 x i32> zeroinitializer)77 ret <4 x i32> %178}79 80define <4 x i32> @test8(<8 x i16> %0) {81; CHECK-LABEL: test8:82; CHECK: # %bb.0: # %entry83; CHECK-NEXT: xxlxor v3, v3, v384; CHECK-NEXT: vsum4shs v2, v2, v385; CHECK-NEXT: blr86entry:87 %1 = tail call <4 x i32> @llvm.ppc.altivec.vsum4shs(<8 x i16> %0, <4 x i32> zeroinitializer)88 ret <4 x i32> %189}90 91define <4 x i32> @test9(<16 x i8> %0) {92; CHECK-LABEL: test9:93; CHECK: # %bb.0: # %entry94; CHECK-NEXT: xxlxor v3, v3, v395; CHECK-NEXT: vsum4ubs v2, v2, v396; CHECK-NEXT: blr97entry:98 %1 = tail call <4 x i32> @llvm.ppc.altivec.vsum4ubs(<16 x i8> %0, <4 x i32> zeroinitializer)99 ret <4 x i32> %1100}101 102define <4 x i32> @test10(<16 x i8> %0, <16 x i8> %1) {103; CHECK-LABEL: test10:104; CHECK: # %bb.0: # %entry105; CHECK-NEXT: xxlxor v3, v3, v3106; CHECK-NEXT: vsum4sbs v2, v2, v3107; CHECK-NEXT: blr108entry:109 %2 = tail call <4 x i32> @llvm.ppc.altivec.vsum4sbs(<16 x i8> %0, <4 x i32> zeroinitializer)110 %3 = tail call <4 x i32> @llvm.ppc.altivec.vsum4sbs(<16 x i8> %1, <4 x i32> zeroinitializer)111 ret <4 x i32> %2112}113 114define <4 x i32> @test11(<8 x i16> %0, <8 x i16> %1) {115; CHECK-LABEL: test11:116; CHECK: # %bb.0: # %entry117; CHECK-NEXT: xxlxor v3, v3, v3118; CHECK-NEXT: vsum4shs v2, v2, v3119; CHECK-NEXT: blr120entry:121 %2 = tail call <4 x i32> @llvm.ppc.altivec.vsum4shs(<8 x i16> %0, <4 x i32> zeroinitializer)122 %3 = tail call <4 x i32> @llvm.ppc.altivec.vsum4shs(<8 x i16> %1, <4 x i32> zeroinitializer)123 ret <4 x i32> %2124}125 126define <4 x i32> @test12(<16 x i8> %0, <16 x i8> %1) {127; CHECK-LABEL: test12:128; CHECK: # %bb.0: # %entry129; CHECK-NEXT: xxlxor v3, v3, v3130; CHECK-NEXT: vsum4ubs v2, v2, v3131; CHECK-NEXT: blr132entry:133 %2 = tail call <4 x i32> @llvm.ppc.altivec.vsum4ubs(<16 x i8> %0, <4 x i32> zeroinitializer)134 %3 = tail call <4 x i32> @llvm.ppc.altivec.vsum4ubs(<16 x i8> %1, <4 x i32> zeroinitializer)135 ret <4 x i32> %2136}137 138declare <4 x i32> @llvm.ppc.altivec.vsum4sbs(<16 x i8>, <4 x i32>)139declare <4 x i32> @llvm.ppc.altivec.vsum4shs(<8 x i16>, <4 x i32>)140declare <4 x i32> @llvm.ppc.altivec.vsum4ubs(<16 x i8>, <4 x i32>)141