25 lines · plain
1; RUN: llc -O0 -mtriple=powerpc-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -verify-machineinstrs < %s | FileCheck %s2; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -verify-machineinstrs -fast-isel=false -mcpu=pwr7 < %s | FileCheck %s3; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -mattr=+vsx -verify-machineinstrs -fast-isel=false -mcpu=pwr7 < %s | FileCheck -check-prefix=CHECK-VSX %s4 5; This verifies that we generate correct spill/reload code for vector regs.6 7define void @addrtaken(i32 %i, <4 x float> %w) nounwind {8entry:9 %i.addr = alloca i32, align 410 %w.addr = alloca <4 x float>, align 1611 store i32 %i, ptr %i.addr, align 412 store <4 x float> %w, ptr %w.addr, align 1613 call void @foo(ptr %i.addr)14 ret void15}16 17; CHECK: stvx 2,18 19; We would prefer to test for "stxvw4x 34," but current -O0 code20; needlessly generates "vor 3,2,2 / stxvw4x 35,0,3", so we'll settle for21; the opcode.22; CHECK-VSX: stxvw4x23 24declare void @foo(ptr)25