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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-unknown | FileCheck %s3 4; First, check the generic pattern for any 2 vector constants. Then, check special cases where5; the constants are all off-by-one. Finally, check the extra special cases where the constants6; include 0 or -1.7; Each minimal select test is repeated with a more typical pattern that includes a compare to8; generate the condition value.9 10define <4 x i32> @sel_C1_or_C2_vec(<4 x i1> %cond) {11; CHECK-LABEL: sel_C1_or_C2_vec:12; CHECK: # %bb.0:13; CHECK-NEXT: addis 3, 2, .LCPI0_0@toc@ha14; CHECK-NEXT: xxleqv 37, 37, 3715; CHECK-NEXT: vslw 2, 2, 516; CHECK-NEXT: addi 3, 3, .LCPI0_0@toc@l17; CHECK-NEXT: vsraw 2, 2, 518; CHECK-NEXT: lxvd2x 0, 0, 319; CHECK-NEXT: addis 3, 2, .LCPI0_1@toc@ha20; CHECK-NEXT: addi 3, 3, .LCPI0_1@toc@l21; CHECK-NEXT: xxswapd 35, 022; CHECK-NEXT: lxvd2x 0, 0, 323; CHECK-NEXT: xxswapd 36, 024; CHECK-NEXT: xxsel 34, 36, 35, 3425; CHECK-NEXT: blr26 %add = select <4 x i1> %cond, <4 x i32> <i32 3000, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>27 ret <4 x i32> %add28}29 30define <4 x i32> @cmp_sel_C1_or_C2_vec(<4 x i32> %x, <4 x i32> %y) {31; CHECK-LABEL: cmp_sel_C1_or_C2_vec:32; CHECK: # %bb.0:33; CHECK-NEXT: addis 3, 2, .LCPI1_0@toc@ha34; CHECK-NEXT: vcmpequw 2, 2, 335; CHECK-NEXT: addi 3, 3, .LCPI1_0@toc@l36; CHECK-NEXT: lxvd2x 0, 0, 337; CHECK-NEXT: addis 3, 2, .LCPI1_1@toc@ha38; CHECK-NEXT: addi 3, 3, .LCPI1_1@toc@l39; CHECK-NEXT: xxswapd 36, 040; CHECK-NEXT: lxvd2x 0, 0, 341; CHECK-NEXT: xxswapd 37, 042; CHECK-NEXT: xxsel 34, 37, 36, 3443; CHECK-NEXT: blr44 %cond = icmp eq <4 x i32> %x, %y45 %add = select <4 x i1> %cond, <4 x i32> <i32 3000, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>46 ret <4 x i32> %add47}48 49define <4 x i32> @sel_Cplus1_or_C_vec(<4 x i1> %cond) {50; CHECK-LABEL: sel_Cplus1_or_C_vec:51; CHECK: # %bb.0:52; CHECK-NEXT: addis 3, 2, .LCPI2_0@toc@ha53; CHECK-NEXT: vspltisw 3, 154; CHECK-NEXT: addi 3, 3, .LCPI2_0@toc@l55; CHECK-NEXT: xxland 34, 34, 3556; CHECK-NEXT: lxvd2x 0, 0, 357; CHECK-NEXT: xxswapd 36, 058; CHECK-NEXT: vadduwm 2, 2, 459; CHECK-NEXT: blr60 %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>61 ret <4 x i32> %add62}63 64define <4 x i32> @cmp_sel_Cplus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) {65; CHECK-LABEL: cmp_sel_Cplus1_or_C_vec:66; CHECK: # %bb.0:67; CHECK-NEXT: addis 3, 2, .LCPI3_0@toc@ha68; CHECK-NEXT: vcmpequw 2, 2, 369; CHECK-NEXT: addi 3, 3, .LCPI3_0@toc@l70; CHECK-NEXT: lxvd2x 0, 0, 371; CHECK-NEXT: xxswapd 36, 072; CHECK-NEXT: vsubuwm 2, 4, 273; CHECK-NEXT: blr74 %cond = icmp eq <4 x i32> %x, %y75 %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>76 ret <4 x i32> %add77}78 79define <4 x i32> @sel_Cminus1_or_C_vec(<4 x i1> %cond) {80; CHECK-LABEL: sel_Cminus1_or_C_vec:81; CHECK: # %bb.0:82; CHECK-NEXT: addis 3, 2, .LCPI4_0@toc@ha83; CHECK-NEXT: xxleqv 36, 36, 3684; CHECK-NEXT: vslw 2, 2, 485; CHECK-NEXT: addi 3, 3, .LCPI4_0@toc@l86; CHECK-NEXT: vsraw 2, 2, 487; CHECK-NEXT: lxvd2x 0, 0, 388; CHECK-NEXT: xxswapd 35, 089; CHECK-NEXT: vadduwm 2, 2, 390; CHECK-NEXT: blr91 %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 44, i32 2, i32 0, i32 1>92 ret <4 x i32> %add93}94 95define <4 x i32> @cmp_sel_Cminus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) {96; CHECK-LABEL: cmp_sel_Cminus1_or_C_vec:97; CHECK: # %bb.0:98; CHECK-NEXT: addis 3, 2, .LCPI5_0@toc@ha99; CHECK-NEXT: vcmpequw 2, 2, 3100; CHECK-NEXT: addi 3, 3, .LCPI5_0@toc@l101; CHECK-NEXT: lxvd2x 0, 0, 3102; CHECK-NEXT: xxswapd 36, 0103; CHECK-NEXT: vadduwm 2, 2, 4104; CHECK-NEXT: blr105 %cond = icmp eq <4 x i32> %x, %y106 %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 44, i32 2, i32 0, i32 1>107 ret <4 x i32> %add108}109 110define <4 x i32> @sel_minus1_or_0_vec(<4 x i1> %cond) {111; CHECK-LABEL: sel_minus1_or_0_vec:112; CHECK: # %bb.0:113; CHECK-NEXT: xxleqv 35, 35, 35114; CHECK-NEXT: vslw 2, 2, 3115; CHECK-NEXT: vsraw 2, 2, 3116; CHECK-NEXT: blr117 %add = select <4 x i1> %cond, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>118 ret <4 x i32> %add119}120 121define <4 x i32> @cmp_sel_minus1_or_0_vec(<4 x i32> %x, <4 x i32> %y) {122; CHECK-LABEL: cmp_sel_minus1_or_0_vec:123; CHECK: # %bb.0:124; CHECK-NEXT: vcmpequw 2, 2, 3125; CHECK-NEXT: blr126 %cond = icmp eq <4 x i32> %x, %y127 %add = select <4 x i1> %cond, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>128 ret <4 x i32> %add129}130 131define <4 x i32> @sel_0_or_minus1_vec(<4 x i1> %cond) {132; CHECK-LABEL: sel_0_or_minus1_vec:133; CHECK: # %bb.0:134; CHECK-NEXT: vspltisw 3, 1135; CHECK-NEXT: xxland 34, 34, 35136; CHECK-NEXT: xxleqv 35, 35, 35137; CHECK-NEXT: vadduwm 2, 2, 3138; CHECK-NEXT: blr139 %add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>140 ret <4 x i32> %add141}142 143define <4 x i32> @cmp_sel_0_or_minus1_vec(<4 x i32> %x, <4 x i32> %y) {144; CHECK-LABEL: cmp_sel_0_or_minus1_vec:145; CHECK: # %bb.0:146; CHECK-NEXT: vcmpequw 2, 2, 3147; CHECK-NEXT: xxlnor 34, 34, 34148; CHECK-NEXT: blr149 %cond = icmp eq <4 x i32> %x, %y150 %add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>151 ret <4 x i32> %add152}153 154define <4 x i32> @sel_1_or_0_vec(<4 x i1> %cond) {155; CHECK-LABEL: sel_1_or_0_vec:156; CHECK: # %bb.0:157; CHECK-NEXT: vspltisw 3, 1158; CHECK-NEXT: xxland 34, 34, 35159; CHECK-NEXT: blr160 %add = select <4 x i1> %cond, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>161 ret <4 x i32> %add162}163 164define <4 x i32> @cmp_sel_1_or_0_vec(<4 x i32> %x, <4 x i32> %y) {165; CHECK-LABEL: cmp_sel_1_or_0_vec:166; CHECK: # %bb.0:167; CHECK-NEXT: vspltisw 4, 1168; CHECK-NEXT: vcmpequw 2, 2, 3169; CHECK-NEXT: xxland 34, 34, 36170; CHECK-NEXT: blr171 %cond = icmp eq <4 x i32> %x, %y172 %add = select <4 x i1> %cond, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>173 ret <4 x i32> %add174}175 176define <4 x i32> @sel_0_or_1_vec(<4 x i1> %cond) {177; CHECK-LABEL: sel_0_or_1_vec:178; CHECK: # %bb.0:179; CHECK-NEXT: vspltisw 3, 1180; CHECK-NEXT: xxlandc 34, 35, 34181; CHECK-NEXT: blr182 %add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 1, i32 1, i32 1, i32 1>183 ret <4 x i32> %add184}185 186define <4 x i32> @cmp_sel_0_or_1_vec(<4 x i32> %x, <4 x i32> %y) {187; CHECK-LABEL: cmp_sel_0_or_1_vec:188; CHECK: # %bb.0:189; CHECK-NEXT: vcmpequw 2, 2, 3190; CHECK-NEXT: vspltisw 4, 1191; CHECK-NEXT: xxlnor 0, 34, 34192; CHECK-NEXT: xxland 34, 0, 36193; CHECK-NEXT: blr194 %cond = icmp eq <4 x i32> %x, %y195 %add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 1, i32 1, i32 1, i32 1>196 ret <4 x i32> %add197}198 199