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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52 3; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-linux-gnu \4; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=POWER10-LE5 6; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64-ibm-aix-xcoff \7; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=POWER10-BE8 9; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc-ibm-aix-xcoff \10; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=POWER3210-BE11 12; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \13; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=POWER9-LE14 15; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-ibm-aix-xcoff \16; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=POWER9-BE17 18; Test VSRO + VSR peephole optimization to VSRQ on Power10+19; This should combine consecutive VSRO (Vector Shift Right Octet) and VSR (Vector Shift Right)20; instructions using the same shift amount into a single VSRQ (Vector Shift Right Quadword)21; instruction when targeting Power10 or later processors.22declare <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32>, <4 x i32>)23declare <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32>, <4 x i32>)24 25define <16 x i8> @shiftright128_v16i8(<16 x i8> %in, i8 zeroext %sh) {26; POWER10-LE-LABEL: shiftright128_v16i8:27; POWER10-LE: # %bb.0: # %entry28; POWER10-LE-NEXT: mtvsrd v3, r529; POWER10-LE-NEXT: vspltb v3, v3, 730; POWER10-LE-NEXT: vsrq v2, v2, v331; POWER10-LE-NEXT: blr32;33; POWER10-BE-LABEL: shiftright128_v16i8:34; POWER10-BE: # %bb.0: # %entry35; POWER10-BE-NEXT: mtvsrwz v3, r336; POWER10-BE-NEXT: vspltb v3, v3, 737; POWER10-BE-NEXT: vsrq v2, v2, v338; POWER10-BE-NEXT: blr39;40; POWER3210-BE-LABEL: shiftright128_v16i8:41; POWER3210-BE: # %bb.0: # %entry42; POWER3210-BE-NEXT: mtvsrwz v3, r343; POWER3210-BE-NEXT: vspltb v3, v3, 744; POWER3210-BE-NEXT: vsrq v2, v2, v345; POWER3210-BE-NEXT: blr46;47; POWER9-LE-LABEL: shiftright128_v16i8:48; POWER9-LE: # %bb.0: # %entry49; POWER9-LE-NEXT: mtvsrd v3, r550; POWER9-LE-NEXT: vspltb v3, v3, 751; POWER9-LE-NEXT: vsro v2, v2, v352; POWER9-LE-NEXT: vsr v2, v2, v353; POWER9-LE-NEXT: blr54;55; POWER9-BE-LABEL: shiftright128_v16i8:56; POWER9-BE: # %bb.0: # %entry57; POWER9-BE-NEXT: mtvsrwz v3, r358; POWER9-BE-NEXT: vspltb v3, v3, 759; POWER9-BE-NEXT: vsro v2, v2, v360; POWER9-BE-NEXT: vsr v2, v2, v361; POWER9-BE-NEXT: blr62entry:63 %splat.splatinsert.i = insertelement <16 x i8> poison, i8 %sh, i64 064 %splat.splat.i = shufflevector <16 x i8> %splat.splatinsert.i, <16 x i8> poison, <16 x i32> zeroinitializer65 %0 = bitcast <16 x i8> %in to <4 x i32>66 %1 = bitcast <16 x i8> %splat.splat.i to <4 x i32>67 %2 = tail call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %0, <4 x i32> %1)68 %3 = tail call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %2, <4 x i32> %1)69 %4 = bitcast <4 x i32> %3 to <16 x i8>70 ret <16 x i8> %471}72 73define <4 x i32> @shiftright128_v4i32(<4 x i32> %in, i8 zeroext %sh) {74; POWER10-LE-LABEL: shiftright128_v4i32:75; POWER10-LE: # %bb.0: # %entry76; POWER10-LE-NEXT: mtvsrd v3, r577; POWER10-LE-NEXT: vspltb v3, v3, 778; POWER10-LE-NEXT: vsrq v2, v2, v379; POWER10-LE-NEXT: blr80;81; POWER10-BE-LABEL: shiftright128_v4i32:82; POWER10-BE: # %bb.0: # %entry83; POWER10-BE-NEXT: mtvsrwz v3, r384; POWER10-BE-NEXT: vspltb v3, v3, 785; POWER10-BE-NEXT: vsrq v2, v2, v386; POWER10-BE-NEXT: blr87;88; POWER3210-BE-LABEL: shiftright128_v4i32:89; POWER3210-BE: # %bb.0: # %entry90; POWER3210-BE-NEXT: mtvsrwz v3, r391; POWER3210-BE-NEXT: vspltb v3, v3, 792; POWER3210-BE-NEXT: vsrq v2, v2, v393; POWER3210-BE-NEXT: blr94;95; POWER9-LE-LABEL: shiftright128_v4i32:96; POWER9-LE: # %bb.0: # %entry97; POWER9-LE-NEXT: mtvsrd v3, r598; POWER9-LE-NEXT: vspltb v3, v3, 799; POWER9-LE-NEXT: vsro v2, v2, v3100; POWER9-LE-NEXT: vsr v2, v2, v3101; POWER9-LE-NEXT: blr102;103; POWER9-BE-LABEL: shiftright128_v4i32:104; POWER9-BE: # %bb.0: # %entry105; POWER9-BE-NEXT: mtvsrwz v3, r3106; POWER9-BE-NEXT: vspltb v3, v3, 7107; POWER9-BE-NEXT: vsro v2, v2, v3108; POWER9-BE-NEXT: vsr v2, v2, v3109; POWER9-BE-NEXT: blr110entry:111 %splat.splatinsert.i = insertelement <16 x i8> poison, i8 %sh, i64 0112 %splat.splat.i = shufflevector <16 x i8> %splat.splatinsert.i, <16 x i8> poison, <16 x i32> zeroinitializer113 %0 = bitcast <16 x i8> %splat.splat.i to <4 x i32>114 %1 = tail call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %in, <4 x i32> %0)115 %2 = tail call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %1, <4 x i32> %0)116 ret <4 x i32> %2117}118 119define <2 x i64> @shiftright128_v2i64(<2 x i64> %in, i8 zeroext %sh) {120; POWER10-LE-LABEL: shiftright128_v2i64:121; POWER10-LE: # %bb.0: # %entry122; POWER10-LE-NEXT: mtvsrd v3, r5123; POWER10-LE-NEXT: vspltb v3, v3, 7124; POWER10-LE-NEXT: vsrq v2, v2, v3125; POWER10-LE-NEXT: blr126;127; POWER10-BE-LABEL: shiftright128_v2i64:128; POWER10-BE: # %bb.0: # %entry129; POWER10-BE-NEXT: mtvsrwz v3, r3130; POWER10-BE-NEXT: vspltb v3, v3, 7131; POWER10-BE-NEXT: vsrq v2, v2, v3132; POWER10-BE-NEXT: blr133;134; POWER3210-BE-LABEL: shiftright128_v2i64:135; POWER3210-BE: # %bb.0: # %entry136; POWER3210-BE-NEXT: mtvsrwz v3, r3137; POWER3210-BE-NEXT: vspltb v3, v3, 7138; POWER3210-BE-NEXT: vsrq v2, v2, v3139; POWER3210-BE-NEXT: blr140;141; POWER9-LE-LABEL: shiftright128_v2i64:142; POWER9-LE: # %bb.0: # %entry143; POWER9-LE-NEXT: mtvsrd v3, r5144; POWER9-LE-NEXT: vspltb v3, v3, 7145; POWER9-LE-NEXT: vsro v2, v2, v3146; POWER9-LE-NEXT: vsr v2, v2, v3147; POWER9-LE-NEXT: blr148;149; POWER9-BE-LABEL: shiftright128_v2i64:150; POWER9-BE: # %bb.0: # %entry151; POWER9-BE-NEXT: mtvsrwz v3, r3152; POWER9-BE-NEXT: vspltb v3, v3, 7153; POWER9-BE-NEXT: vsro v2, v2, v3154; POWER9-BE-NEXT: vsr v2, v2, v3155; POWER9-BE-NEXT: blr156entry:157 %splat.splatinsert.i = insertelement <16 x i8> poison, i8 %sh, i64 0158 %splat.splat.i = shufflevector <16 x i8> %splat.splatinsert.i, <16 x i8> poison, <16 x i32> zeroinitializer159 %0 = bitcast <2 x i64> %in to <4 x i32>160 %1 = bitcast <16 x i8> %splat.splat.i to <4 x i32>161 %2 = tail call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %0, <4 x i32> %1)162 %3 = tail call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %2, <4 x i32> %1)163 %4 = bitcast <4 x i32> %3 to <2 x i64>164 ret <2 x i64> %4165}166 167define <8 x i16> @shiftright128_v8i16(<8 x i16> %in, i8 zeroext %sh) {168; POWER10-LE-LABEL: shiftright128_v8i16:169; POWER10-LE: # %bb.0: # %entry170; POWER10-LE-NEXT: mtvsrd v3, r5171; POWER10-LE-NEXT: vspltb v3, v3, 7172; POWER10-LE-NEXT: vsrq v2, v2, v3173; POWER10-LE-NEXT: blr174;175; POWER10-BE-LABEL: shiftright128_v8i16:176; POWER10-BE: # %bb.0: # %entry177; POWER10-BE-NEXT: mtvsrwz v3, r3178; POWER10-BE-NEXT: vspltb v3, v3, 7179; POWER10-BE-NEXT: vsrq v2, v2, v3180; POWER10-BE-NEXT: blr181;182; POWER3210-BE-LABEL: shiftright128_v8i16:183; POWER3210-BE: # %bb.0: # %entry184; POWER3210-BE-NEXT: mtvsrwz v3, r3185; POWER3210-BE-NEXT: vspltb v3, v3, 7186; POWER3210-BE-NEXT: vsrq v2, v2, v3187; POWER3210-BE-NEXT: blr188;189; POWER9-LE-LABEL: shiftright128_v8i16:190; POWER9-LE: # %bb.0: # %entry191; POWER9-LE-NEXT: mtvsrd v3, r5192; POWER9-LE-NEXT: vspltb v3, v3, 7193; POWER9-LE-NEXT: vsro v2, v2, v3194; POWER9-LE-NEXT: vsr v2, v2, v3195; POWER9-LE-NEXT: blr196;197; POWER9-BE-LABEL: shiftright128_v8i16:198; POWER9-BE: # %bb.0: # %entry199; POWER9-BE-NEXT: mtvsrwz v3, r3200; POWER9-BE-NEXT: vspltb v3, v3, 7201; POWER9-BE-NEXT: vsro v2, v2, v3202; POWER9-BE-NEXT: vsr v2, v2, v3203; POWER9-BE-NEXT: blr204entry:205 %splat.splatinsert.i = insertelement <16 x i8> poison, i8 %sh, i64 0206 %splat.splat.i = shufflevector <16 x i8> %splat.splatinsert.i, <16 x i8> poison, <16 x i32> zeroinitializer207 %0 = bitcast <8 x i16> %in to <4 x i32>208 %1 = bitcast <16 x i8> %splat.splat.i to <4 x i32>209 %2 = tail call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %0, <4 x i32> %1)210 %3 = tail call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %2, <4 x i32> %1)211 %4 = bitcast <4 x i32> %3 to <8 x i16>212 ret <8 x i16> %4213}214 215; Test case with different vectors (should not optimize - different shift amount registers)216define <16 x i8> @no_optimization_different_shifts(<16 x i8> %in, i8 zeroext %sh1, i8 zeroext %sh2) {217; POWER10-LE-LABEL: no_optimization_different_shifts:218; POWER10-LE: # %bb.0: # %entry219; POWER10-LE-NEXT: mtvsrd v3, r5220; POWER10-LE-NEXT: mtvsrd v4, r6221; POWER10-LE-NEXT: vspltb v3, v3, 7222; POWER10-LE-NEXT: vspltb v4, v4, 7223; POWER10-LE-NEXT: vsro v2, v2, v3224; POWER10-LE-NEXT: vsr v2, v2, v4225; POWER10-LE-NEXT: blr226;227; POWER10-BE-LABEL: no_optimization_different_shifts:228; POWER10-BE: # %bb.0: # %entry229; POWER10-BE-NEXT: mtvsrwz v3, r3230; POWER10-BE-NEXT: mtvsrwz v4, r4231; POWER10-BE-NEXT: vspltb v3, v3, 7232; POWER10-BE-NEXT: vspltb v4, v4, 7233; POWER10-BE-NEXT: vsro v2, v2, v3234; POWER10-BE-NEXT: vsr v2, v2, v4235; POWER10-BE-NEXT: blr236;237; POWER3210-BE-LABEL: no_optimization_different_shifts:238; POWER3210-BE: # %bb.0: # %entry239; POWER3210-BE-NEXT: mtvsrwz v3, r3240; POWER3210-BE-NEXT: mtvsrwz v4, r4241; POWER3210-BE-NEXT: vspltb v3, v3, 7242; POWER3210-BE-NEXT: vspltb v4, v4, 7243; POWER3210-BE-NEXT: vsro v2, v2, v3244; POWER3210-BE-NEXT: vsr v2, v2, v4245; POWER3210-BE-NEXT: blr246;247; POWER9-LE-LABEL: no_optimization_different_shifts:248; POWER9-LE: # %bb.0: # %entry249; POWER9-LE-NEXT: mtvsrd v3, r5250; POWER9-LE-NEXT: mtvsrd v4, r6251; POWER9-LE-NEXT: vspltb v3, v3, 7252; POWER9-LE-NEXT: vspltb v4, v4, 7253; POWER9-LE-NEXT: vsro v2, v2, v3254; POWER9-LE-NEXT: vsr v2, v2, v4255; POWER9-LE-NEXT: blr256;257; POWER9-BE-LABEL: no_optimization_different_shifts:258; POWER9-BE: # %bb.0: # %entry259; POWER9-BE-NEXT: mtvsrwz v3, r3260; POWER9-BE-NEXT: mtvsrwz v4, r4261; POWER9-BE-NEXT: vspltb v3, v3, 7262; POWER9-BE-NEXT: vspltb v4, v4, 7263; POWER9-BE-NEXT: vsro v2, v2, v3264; POWER9-BE-NEXT: vsr v2, v2, v4265; POWER9-BE-NEXT: blr266entry:267 %splat.splatinsert.i = insertelement <16 x i8> poison, i8 %sh1, i64 0268 %splat.splat.i = shufflevector <16 x i8> %splat.splatinsert.i, <16 x i8> poison, <16 x i32> zeroinitializer269 %splat.splatinsert.i2 = insertelement <16 x i8> poison, i8 %sh2, i64 0270 %splat.splat.i2 = shufflevector <16 x i8> %splat.splatinsert.i2, <16 x i8> poison, <16 x i32> zeroinitializer271 %0 = bitcast <16 x i8> %in to <4 x i32>272 %1 = bitcast <16 x i8> %splat.splat.i to <4 x i32>273 %2 = bitcast <16 x i8> %splat.splat.i2 to <4 x i32>274 %3 = tail call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %0, <4 x i32> %1)275 %4 = tail call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %3, <4 x i32> %2)276 %5 = bitcast <4 x i32> %4 to <16 x i8>277 ret <16 x i8> %5278}279 280; Test case with multiple uses of VSRO result (should not optimize)281define <16 x i8> @no_optimization_multiple_uses(<16 x i8> %in, i8 zeroext %sh) {282; POWER10-LE-LABEL: no_optimization_multiple_uses:283; POWER10-LE: # %bb.0: # %entry284; POWER10-LE-NEXT: mtvsrd v3, r5285; POWER10-LE-NEXT: vspltb v3, v3, 7286; POWER10-LE-NEXT: vsro v2, v2, v3287; POWER10-LE-NEXT: vsr v3, v2, v3288; POWER10-LE-NEXT: vaddubm v2, v2, v3289; POWER10-LE-NEXT: blr290;291; POWER10-BE-LABEL: no_optimization_multiple_uses:292; POWER10-BE: # %bb.0: # %entry293; POWER10-BE-NEXT: mtvsrwz v3, r3294; POWER10-BE-NEXT: vspltb v3, v3, 7295; POWER10-BE-NEXT: vsro v2, v2, v3296; POWER10-BE-NEXT: vsr v3, v2, v3297; POWER10-BE-NEXT: vaddubm v2, v2, v3298; POWER10-BE-NEXT: blr299;300; POWER3210-BE-LABEL: no_optimization_multiple_uses:301; POWER3210-BE: # %bb.0: # %entry302; POWER3210-BE-NEXT: mtvsrwz v3, r3303; POWER3210-BE-NEXT: vspltb v3, v3, 7304; POWER3210-BE-NEXT: vsro v2, v2, v3305; POWER3210-BE-NEXT: vsr v3, v2, v3306; POWER3210-BE-NEXT: vaddubm v2, v2, v3307; POWER3210-BE-NEXT: blr308;309; POWER9-LE-LABEL: no_optimization_multiple_uses:310; POWER9-LE: # %bb.0: # %entry311; POWER9-LE-NEXT: mtvsrd v3, r5312; POWER9-LE-NEXT: vspltb v3, v3, 7313; POWER9-LE-NEXT: vsro v2, v2, v3314; POWER9-LE-NEXT: vsr v3, v2, v3315; POWER9-LE-NEXT: vaddubm v2, v2, v3316; POWER9-LE-NEXT: blr317;318; POWER9-BE-LABEL: no_optimization_multiple_uses:319; POWER9-BE: # %bb.0: # %entry320; POWER9-BE-NEXT: mtvsrwz v3, r3321; POWER9-BE-NEXT: vspltb v3, v3, 7322; POWER9-BE-NEXT: vsro v2, v2, v3323; POWER9-BE-NEXT: vsr v3, v2, v3324; POWER9-BE-NEXT: vaddubm v2, v2, v3325; POWER9-BE-NEXT: blr326entry:327 %splat.splatinsert.i = insertelement <16 x i8> poison, i8 %sh, i64 0328 %splat.splat.i = shufflevector <16 x i8> %splat.splatinsert.i, <16 x i8> poison, <16 x i32> zeroinitializer329 %0 = bitcast <16 x i8> %in to <4 x i32>330 %1 = bitcast <16 x i8> %splat.splat.i to <4 x i32>331 %2 = tail call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %0, <4 x i32> %1)332 %3 = tail call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %2, <4 x i32> %1)333 %4 = bitcast <4 x i32> %3 to <16 x i8>334 %5 = bitcast <4 x i32> %2 to <16 x i8>335 %6 = add <16 x i8> %5, %4336 ret <16 x i8> %6337}338