42 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs < %s -mcpu=pwr7 -mattr=+vsx | FileCheck %s3; RUN: llc -verify-machineinstrs < %s -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 | \4; RUN: FileCheck -check-prefix=CHECK-FISL %s5target datalayout = "E-m:e-i64:64-n32:64"6target triple = "powerpc64-unknown-linux-gnu"7 8declare <2 x double> @sv(<2 x double>, <2 x i64>, <4 x float>) #09 10define <2 x double> @main(<4 x float> %a, <2 x double> %b, <2 x i64> %c) #1 {11entry:12 %ca = tail call <2 x double> @sv(<2 x double> %b, <2 x i64> %c, <4 x float> %a)13 %v = fadd <2 x double> %ca, <double 1.0, double 1.0>14 ret <2 x double> %v15 16; CHECK-LABEL: @main17; CHECK-DAG: vmr [[V:[0-9]+]], 218; CHECK-DAG: vmr 2, 319; CHECK-DAG: vmr 3, 420; CHECK-DAG: vmr 4, [[V]]21; CHECK: bl sv22; CHECK: lxvd2x [[VC:[0-9]+]],23; CHECK: xvadddp 34, 34, [[VC]]24; CHECK: blr25 26; CHECK-FISL-LABEL: @main27; CHECK-FISL: stxvd2x 36, 1, 328; CHECK-FISL: vmr 4, 329; CHECK-FISL: lxvd2x 35, 1, 330; CHECK-FISL: 3, 14431; CHECK-FISL: stxvd2x 36, 1, 332; CHECK-FISL: vmr 4, 233; CHECK-FISL: bl sv34 35; CHECK-FISL: lxvd2x [[VC:[0-9]+]],36; CHECK-FISL: xvadddp 34, 34, [[VC]]37; CHECK-FISL: blr38}39 40attributes #0 = { noinline nounwind readnone }41attributes #1 = { nounwind }42