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1; RUN: llc -verify-machineinstrs < %s -mcpu=pwr7 -mattr=+vsx | FileCheck %s2; RUN: llc -verify-machineinstrs < %s -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 | FileCheck -check-prefix=CHECK-FISL %s3; XFAIL: *4 5; Also run with -schedule-ppc-vsx-fma-mutation-early as a stress test for the6; live-interval-updating logic.7; RUN: llc -verify-machineinstrs < %s -mcpu=pwr7 -mattr=+vsx -schedule-ppc-vsx-fma-mutation-early8target datalayout = "E-m:e-i64:64-n32:64"9target triple = "powerpc64-unknown-linux-gnu"10 11define void @test1(double %a, double %b, double %c, double %e, ptr nocapture %d) #0 {12entry:13 %0 = tail call double @llvm.fma.f64(double %b, double %c, double %a)14 store double %0, ptr %d, align 815 %1 = tail call double @llvm.fma.f64(double %b, double %e, double %a)16 %arrayidx1 = getelementptr inbounds double, ptr %d, i64 117 store double %1, ptr %arrayidx1, align 818 ret void19 20; CHECK-LABEL: @test121; CHECK-DAG: li [[C1:[0-9]+]], 822; CHECK-DAG: xsmaddmdp 3, 2, 123; CHECK-DAG: xsmaddadp 1, 2, 424; CHECK-DAG: stxsdx 3, 0, 725; CHECK-DAG: stxsdx 1, 7, [[C1]]26; CHECK: blr27 28; CHECK-FISL-LABEL: @test129; CHECK-FISL-DAG: fmr 0, 130; CHECK-FISL-DAG: xsmaddadp 0, 2, 331; CHECK-FISL-DAG: stxsdx 0, 0, 732; CHECK-FISL-DAG: xsmaddadp 1, 2, 433; CHECK-FISL-DAG: li [[C1:[0-9]+]], 834; CHECK-FISL-DAG: stxsdx 1, 7, [[C1]]35; CHECK-FISL: blr36}37 38define void @test2(double %a, double %b, double %c, double %e, double %f, ptr nocapture %d) #0 {39entry:40 %0 = tail call double @llvm.fma.f64(double %b, double %c, double %a)41 store double %0, ptr %d, align 842 %1 = tail call double @llvm.fma.f64(double %b, double %e, double %a)43 %arrayidx1 = getelementptr inbounds double, ptr %d, i64 144 store double %1, ptr %arrayidx1, align 845 %2 = tail call double @llvm.fma.f64(double %b, double %f, double %a)46 %arrayidx2 = getelementptr inbounds double, ptr %d, i64 247 store double %2, ptr %arrayidx2, align 848 ret void49 50; CHECK-LABEL: @test251; CHECK-DAG: li [[C1:[0-9]+]], 852; CHECK-DAG: li [[C2:[0-9]+]], 1653; FIXME: We no longer get this because of copy ordering at the MI level.54; CHECX-DAG: xsmaddmdp 3, 2, 155; CHECX-DAG: xsmaddmdp 4, 2, 156; CHECX-DAG: xsmaddadp 1, 2, 557; CHECX-DAG: stxsdx 3, 0, 858; CHECX-DAG: stxsdx 4, 8, [[C1]]59; CHECX-DAG: stxsdx 1, 8, [[C2]]60; CHECK: blr61 62; CHECK-FISL-LABEL: @test263; CHECK-FISL-DAG: fmr 0, 164; CHECK-FISL-DAG: xsmaddadp 0, 2, 365; CHECK-FISL-DAG: stxsdx 0, 0, 866; CHECK-FISL-DAG: fmr 0, 167; CHECK-FISL-DAG: xsmaddadp 0, 2, 468; CHECK-FISL-DAG: li [[C1:[0-9]+]], 869; CHECK-FISL-DAG: stxsdx 0, 8, [[C1]]70; CHECK-FISL-DAG: xsmaddadp 1, 2, 571; CHECK-FISL-DAG: li [[C2:[0-9]+]], 1672; CHECK-FISL-DAG: stxsdx 1, 8, [[C2]]73; CHECK-FISL: blr74}75 76define void @test3(double %a, double %b, double %c, double %e, double %f, ptr nocapture %d) #0 {77entry:78 %0 = tail call double @llvm.fma.f64(double %b, double %c, double %a)79 store double %0, ptr %d, align 880 %1 = tail call double @llvm.fma.f64(double %b, double %e, double %a)81 %2 = tail call double @llvm.fma.f64(double %b, double %c, double %1)82 %arrayidx1 = getelementptr inbounds double, ptr %d, i64 383 store double %2, ptr %arrayidx1, align 884 %3 = tail call double @llvm.fma.f64(double %b, double %f, double %a)85 %arrayidx2 = getelementptr inbounds double, ptr %d, i64 286 store double %3, ptr %arrayidx2, align 887 %arrayidx3 = getelementptr inbounds double, ptr %d, i64 188 store double %1, ptr %arrayidx3, align 889 ret void90 91; CHECK-LABEL: @test392; CHECK-DAG: fmr [[F1:[0-9]+]], 193; CHECK-DAG: li [[C1:[0-9]+]], 2494; CHECK-DAG: li [[C2:[0-9]+]], 1695; CHECK-DAG: li [[C3:[0-9]+]], 896; CHECK-DAG: xsmaddmdp 4, 2, 197; CHECK-DAG: xsmaddadp 1, 2, 598 99; Note: We could convert this next FMA to M-type as well, but it would require100; re-ordering the instructions.101; CHECK-DAG: xsmaddadp [[F1]], 2, 3102 103; CHECK-DAG: xsmaddmdp 3, 2, 4104; CHECK-DAG: stxsdx [[F1]], 0, 8105; CHECK-DAG: stxsdx 3, 8, [[C1]]106; CHECK-DAG: stxsdx 1, 8, [[C2]]107; CHECK-DAG: stxsdx 4, 8, [[C3]]108; CHECK: blr109 110; CHECK-FISL-LABEL: @test3111; CHECK-FISL-DAG: fmr [[F1:[0-9]+]], 1112; CHECK-FISL-DAG: xsmaddadp [[F1]], 2, 4113; CHECK-FISL-DAG: fmr 4, [[F1]]114; CHECK-FISL-DAG: xsmaddadp 4, 2, 3115; CHECK-FISL-DAG: li [[C1:[0-9]+]], 24116; CHECK-FISL-DAG: stxsdx 4, 8, [[C1]]117; CHECK-FISL-DAG: xsmaddadp 1, 2, 5118; CHECK-FISL-DAG: li [[C2:[0-9]+]], 16119; CHECK-FISL-DAG: stxsdx 1, 8, [[C2]]120; CHECK-FISL-DAG: li [[C3:[0-9]+]], 8121; CHECK-FISL-DAG: stxsdx 0, 8, [[C3]]122; CHECK-FISL: blr123}124 125define void @test4(double %a, double %b, double %c, double %e, double %f, ptr nocapture %d) #0 {126entry:127 %0 = tail call double @llvm.fma.f64(double %b, double %c, double %a)128 store double %0, ptr %d, align 8129 %1 = tail call double @llvm.fma.f64(double %b, double %e, double %a)130 %arrayidx1 = getelementptr inbounds double, ptr %d, i64 1131 store double %1, ptr %arrayidx1, align 8132 %2 = tail call double @llvm.fma.f64(double %b, double %c, double %1)133 %arrayidx3 = getelementptr inbounds double, ptr %d, i64 3134 store double %2, ptr %arrayidx3, align 8135 %3 = tail call double @llvm.fma.f64(double %b, double %f, double %a)136 %arrayidx4 = getelementptr inbounds double, ptr %d, i64 2137 store double %3, ptr %arrayidx4, align 8138 ret void139 140; CHECK-LABEL: @test4141; CHECK-DAG: fmr [[F1:[0-9]+]], 1142; CHECK-DAG: li [[C1:[0-9]+]], 8143; CHECK-DAG: li [[C2:[0-9]+]], 16144; CHECK-DAG: xsmaddmdp 4, 2, 1145 146; Note: We could convert this next FMA to M-type as well, but it would require147; re-ordering the instructions.148; CHECK-DAG: xsmaddadp 1, 2, 5149 150; CHECK-DAG: xsmaddadp [[F1]], 2, 3151; CHECK-DAG: stxsdx [[F1]], 0, 8152; CHECK-DAG: stxsdx 4, 8, [[C1]]153; CHECK-DAG: li [[C3:[0-9]+]], 24154; CHECK-DAG: xsmaddadp 4, 2, 3155; CHECK-DAG: stxsdx 4, 8, [[C3]]156; CHECK-DAG: stxsdx 1, 8, [[C2]]157; CHECK: blr158 159; CHECK-FISL-LABEL: @test4160; CHECK-FISL-DAG: fmr [[F1:[0-9]+]], 1161; CHECK-FISL-DAG: xsmaddadp [[F1]], 2, 3162; CHECK-FISL-DAG: stxsdx 0, 0, 8163; CHECK-FISL-DAG: fmr [[F1]], 1164; CHECK-FISL-DAG: xsmaddadp [[F1]], 2, 4165; CHECK-FISL-DAG: li [[C3:[0-9]+]], 8166; CHECK-FISL-DAG: stxsdx 0, 8, [[C3]]167; CHECK-FISL-DAG: xsmaddadp 0, 2, 3168; CHECK-FISL-DAG: li [[C1:[0-9]+]], 24169; CHECK-FISL-DAG: stxsdx 0, 8, [[C1]]170; CHECK-FISL-DAG: xsmaddadp 1, 2, 5171; CHECK-FISL-DAG: li [[C2:[0-9]+]], 16172; CHECK-FISL-DAG: stxsdx 1, 8, [[C2]]173; CHECK-FISL: blr174}175 176declare double @llvm.fma.f64(double, double, double) #0177 178define void @testv1(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %e, ptr nocapture %d) #0 {179entry:180 %0 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %c, <2 x double> %a)181 store <2 x double> %0, ptr %d, align 8182 %1 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %e, <2 x double> %a)183 %arrayidx1 = getelementptr inbounds <2 x double>, ptr %d, i64 1184 store <2 x double> %1, ptr %arrayidx1, align 8185 ret void186 187; CHECK-LABEL: @testv1188; CHECK-DAG: xvmaddmdp 36, 35, 34189; CHECK-DAG: xvmaddadp 34, 35, 37190; CHECK-DAG: li [[C1:[0-9]+]], 16191; CHECK-DAG: stxvd2x 36, 0, 3192; CHECK-DAG: stxvd2x 34, 3, [[C1:[0-9]+]]193; CHECK: blr194 195; CHECK-FISL-LABEL: @testv1196; CHECK-FISL-DAG: xxlor 0, 34, 34197; CHECK-FISL-DAG: xvmaddadp 0, 35, 36198; CHECK-FISL-DAG: stxvd2x 0, 0, 3199; CHECK-FISL-DAG: xvmaddadp 34, 35, 37200; CHECK-FISL-DAG: li [[C1:[0-9]+]], 16201; CHECK-FISL-DAG: stxvd2x 34, 3, [[C1:[0-9]+]]202; CHECK-FISL: blr203}204 205define void @testv2(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %e, <2 x double> %f, ptr nocapture %d) #0 {206entry:207 %0 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %c, <2 x double> %a)208 store <2 x double> %0, ptr %d, align 8209 %1 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %e, <2 x double> %a)210 %arrayidx1 = getelementptr inbounds <2 x double>, ptr %d, i64 1211 store <2 x double> %1, ptr %arrayidx1, align 8212 %2 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %f, <2 x double> %a)213 %arrayidx2 = getelementptr inbounds <2 x double>, ptr %d, i64 2214 store <2 x double> %2, ptr %arrayidx2, align 8215 ret void216 217; CHECK-LABEL: @testv2218; FIXME: We currently don't get this because of copy ordering on the MI level.219; CHECX-DAG: xvmaddmdp 36, 35, 34220; CHECX-DAG: xvmaddmdp 37, 35, 34221; CHECX-DAG: li [[C1:[0-9]+]], 16222; CHECX-DAG: li [[C2:[0-9]+]], 32223; CHECX-DAG: xvmaddadp 34, 35, 38224; CHECX-DAG: stxvd2x 36, 0, 3225; CHECX-DAG: stxvd2x 37, 3, [[C1:[0-9]+]]226; CHECX-DAG: stxvd2x 34, 3, [[C2:[0-9]+]]227; CHECK: blr228 229; CHECK-FISL-LABEL: @testv2230; CHECK-FISL-DAG: xxlor 0, 34, 34231; CHECK-FISL-DAG: xvmaddadp 0, 35, 36232; CHECK-FISL-DAG: stxvd2x 0, 0, 3233; CHECK-FISL-DAG: xxlor 0, 34, 34234; CHECK-FISL-DAG: xvmaddadp 0, 35, 37235; CHECK-FISL-DAG: li [[C1:[0-9]+]], 16236; CHECK-FISL-DAG: stxvd2x 0, 3, [[C1:[0-9]+]]237; CHECK-FISL-DAG: xvmaddadp 34, 35, 38238; CHECK-FISL-DAG: li [[C2:[0-9]+]], 32239; CHECK-FISL-DAG: stxvd2x 34, 3, [[C2:[0-9]+]]240; CHECK-FISL: blr241}242 243define void @testv3(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %e, <2 x double> %f, ptr nocapture %d) #0 {244entry:245 %0 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %c, <2 x double> %a)246 store <2 x double> %0, ptr %d, align 8247 %1 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %e, <2 x double> %a)248 %2 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %c, <2 x double> %1)249 %arrayidx1 = getelementptr inbounds <2 x double>, ptr %d, i64 3250 store <2 x double> %2, ptr %arrayidx1, align 8251 %3 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %f, <2 x double> %a)252 %arrayidx2 = getelementptr inbounds <2 x double>, ptr %d, i64 2253 store <2 x double> %3, ptr %arrayidx2, align 8254 %arrayidx3 = getelementptr inbounds <2 x double>, ptr %d, i64 1255 store <2 x double> %1, ptr %arrayidx3, align 8256 ret void257 258; Note: There is some unavoidable changeability in this variant. If the259; FMAs are reordered differently, the algorithm can pick a different260; multiplicand to destroy, changing the register assignment. There isn't261; a good way to express this possibility, so hopefully this doesn't change262; too often.263 264; CHECK-LABEL: @testv3265; CHECK-DAG: xxlor [[V1:[0-9]+]], 34, 34266; CHECK-DAG: li [[C1:[0-9]+]], 48267; CHECK-DAG: li [[C2:[0-9]+]], 32268; CHECK-DAG: xvmaddmdp 37, 35, 34269; CHECK-DAG: li [[C3:[0-9]+]], 16270 271; Note: We could convert this next FMA to M-type as well, but it would require272; re-ordering the instructions.273; CHECK-DAG: xvmaddadp [[V1]], 35, 36274 275; CHECK-DAG: xvmaddmdp 36, 35, 37276; CHECK-DAG: xvmaddadp 34, 35, 38277; CHECK-DAG: stxvd2x 32, 0, 3278; CHECK-DAG: stxvd2x 36, 3, [[C1]]279; CHECK-DAG: stxvd2x 34, 3, [[C2]]280; CHECK-DAG: stxvd2x 37, 3, [[C3]]281; CHECK: blr282 283; CHECK-FISL-LABEL: @testv3284; CHECK-FISL-DAG: xxlor [[V1:[0-9]+]], 34, 34285; CHECK-FISL-DAG: xvmaddadp [[V1]], 35, 36286; CHECK-FISL-DAG: stxvd2x [[V1]], 0, 3287; CHECK-FISL-DAG: xxlor [[V2:[0-9]+]], 34, 34288; CHECK-FISL-DAG: xvmaddadp [[V2]], 35, 37289; CHECK-FISL-DAG: xxlor [[V3:[0-9]+]], 0, 0290; CHECK-FISL-DAG: xvmaddadp [[V3]], 35, 36291; CHECK-FISL-DAG: li [[C1:[0-9]+]], 48292; CHECK-FISL-DAG: stxvd2x [[V3]], 3, [[C1]]293; CHECK-FISL-DAG: xvmaddadp 34, 35, 38294; CHECK-FISL-DAG: li [[C2:[0-9]+]], 32295; CHECK-FISL-DAG: stxvd2x 34, 3, [[C2]]296; CHECK-FISL-DAG: li [[C3:[0-9]+]], 16297; CHECK-FISL-DAG: stxvd2x 0, 3, [[C3]]298; CHECK-FISL: blr299}300 301define void @testv4(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %e, <2 x double> %f, ptr nocapture %d) #0 {302entry:303 %0 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %c, <2 x double> %a)304 store <2 x double> %0, ptr %d, align 8305 %1 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %e, <2 x double> %a)306 %arrayidx1 = getelementptr inbounds <2 x double>, ptr %d, i64 1307 store <2 x double> %1, ptr %arrayidx1, align 8308 %2 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %c, <2 x double> %1)309 %arrayidx3 = getelementptr inbounds <2 x double>, ptr %d, i64 3310 store <2 x double> %2, ptr %arrayidx3, align 8311 %3 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %f, <2 x double> %a)312 %arrayidx4 = getelementptr inbounds <2 x double>, ptr %d, i64 2313 store <2 x double> %3, ptr %arrayidx4, align 8314 ret void315 316; CHECK-LABEL: @testv4317; CHECK-DAG: xxlor [[V1:[0-9]+]], 34, 34318; CHECK-DAG: xvmaddmdp 37, 35, 34319; CHECK-DAG: li [[C1:[0-9]+]], 16320; CHECK-DAG: li [[C2:[0-9]+]], 32321; CHECK-DAG: xvmaddadp 34, 35, 38322 323; Note: We could convert this next FMA to M-type as well, but it would require324; re-ordering the instructions.325; CHECK-DAG: xvmaddadp [[V1]], 35, 36326 327; CHECK-DAG: stxvd2x 32, 0, 3328; CHECK-DAG: stxvd2x 37, 3, [[C1]]329; CHECK-DAG: li [[C3:[0-9]+]], 48330; CHECK-DAG: xvmaddadp 37, 35, 36331; CHECK-DAG: stxvd2x 37, 3, [[C3]]332; CHECK-DAG: stxvd2x 34, 3, [[C2]]333; CHECK: blr334 335; CHECK-FISL-LABEL: @testv4336; CHECK-FISL-DAG: xxlor [[V1:[0-9]+]], 34, 34337; CHECK-FISL-DAG: xvmaddadp [[V1]], 35, 36338; CHECK-FISL-DAG: stxvd2x 0, 0, 3339; CHECK-FISL-DAG: xxlor [[V2:[0-9]+]], 34, 34340; CHECK-FISL-DAG: xvmaddadp [[V2]], 35, 37341; CHECK-FISL-DAG: li [[C1:[0-9]+]], 16342; CHECK-FISL-DAG: stxvd2x 0, 3, [[C1]]343; CHECK-FISL-DAG: xvmaddadp 0, 35, 37344; CHECK-FISL-DAG: li [[C3:[0-9]+]], 48345; CHECK-FISL-DAG: stxvd2x 0, 3, [[C3]]346; CHECK-FISL-DAG: xvmaddadp 0, 35, 36347; CHECK-FISL-DAG: li [[C2:[0-9]+]], 32348; CHECK-FISL-DAG: stxvd2x 34, 3, [[C2]]349; CHECK-FISL: blr350}351 352declare <2 x double> @llvm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>) #0353 354attributes #0 = { nounwind readnone }355 356