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1; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=+vsx | FileCheck %s2; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=+vsx -fast-isel -O0 | FileCheck -check-prefix=CHECK-FISL %s3; XFAIL: *4 5define void @test1sp(float %a, float %b, float %c, float %e, ptr nocapture %d) #0 {6entry:7 %0 = tail call float @llvm.fma.f32(float %b, float %c, float %a)8 store float %0, ptr %d, align 49 %1 = tail call float @llvm.fma.f32(float %b, float %e, float %a)10 %arrayidx1 = getelementptr inbounds float, ptr %d, i64 111 store float %1, ptr %arrayidx1, align 412 ret void13 14; CHECK-LABEL: @test1sp15; CHECK-DAG: li [[C1:[0-9]+]], 416; CHECK-DAG: xsmaddmsp 3, 2, 117; CHECK-DAG: xsmaddasp 1, 2, 418; CHECK-DAG: stxsspx 3, 0, 719; CHECK-DAG: stxsspx 1, 7, [[C1]]20; CHECK: blr21 22; CHECK-FISL-LABEL: @test1sp23; CHECK-FISL-DAG: fmr 0, 124; CHECK-FISL-DAG: xsmaddasp 0, 2, 325; CHECK-FISL-DAG: stxsspx 0, 0, 726; CHECK-FISL-DAG: xsmaddasp 1, 2, 427; CHECK-FISL-DAG: li [[C1:[0-9]+]], 428; CHECK-FISL-DAG: stxsspx 1, 7, [[C1]]29; CHECK-FISL: blr30}31 32define void @test2sp(float %a, float %b, float %c, float %e, float %f, ptr nocapture %d) #0 {33entry:34 %0 = tail call float @llvm.fma.f32(float %b, float %c, float %a)35 store float %0, ptr %d, align 436 %1 = tail call float @llvm.fma.f32(float %b, float %e, float %a)37 %arrayidx1 = getelementptr inbounds float, ptr %d, i64 138 store float %1, ptr %arrayidx1, align 439 %2 = tail call float @llvm.fma.f32(float %b, float %f, float %a)40 %arrayidx2 = getelementptr inbounds float, ptr %d, i64 241 store float %2, ptr %arrayidx2, align 442 ret void43 44; CHECK-LABEL: @test2sp45; CHECK-DAG: li [[C1:[0-9]+]], 446; CHECK-DAG: li [[C2:[0-9]+]], 847; FIXME: We now miss this because of copy ordering at the MI level.48; CHECX-DAG: xsmaddmsp 3, 2, 149; CHECX-DAG: xsmaddmsp 4, 2, 150; CHECX-DAG: xsmaddasp 1, 2, 551; CHECX-DAG: stxsspx 3, 0, 852; CHECX-DAG: stxsspx 4, 8, [[C1]]53; CHECX-DAG: stxsspx 1, 8, [[C2]]54; CHECK: blr55 56; CHECK-FISL-LABEL: @test2sp57; CHECK-FISL-DAG: fmr 0, 158; CHECK-FISL-DAG: xsmaddasp 0, 2, 359; CHECK-FISL-DAG: stxsspx 0, 0, 860; CHECK-FISL-DAG: fmr 0, 161; CHECK-FISL-DAG: xsmaddasp 0, 2, 462; CHECK-FISL-DAG: li [[C1:[0-9]+]], 463; CHECK-FISL-DAG: stxsspx 0, 8, [[C1]]64; CHECK-FISL-DAG: xsmaddasp 1, 2, 565; CHECK-FISL-DAG: li [[C2:[0-9]+]], 866; CHECK-FISL-DAG: stxsspx 1, 8, [[C2]]67; CHECK-FISL: blr68}69 70define void @test3sp(float %a, float %b, float %c, float %e, float %f, ptr nocapture %d) #0 {71entry:72 %0 = tail call float @llvm.fma.f32(float %b, float %c, float %a)73 store float %0, ptr %d, align 474 %1 = tail call float @llvm.fma.f32(float %b, float %e, float %a)75 %2 = tail call float @llvm.fma.f32(float %b, float %c, float %1)76 %arrayidx1 = getelementptr inbounds float, ptr %d, i64 377 store float %2, ptr %arrayidx1, align 478 %3 = tail call float @llvm.fma.f32(float %b, float %f, float %a)79 %arrayidx2 = getelementptr inbounds float, ptr %d, i64 280 store float %3, ptr %arrayidx2, align 481 %arrayidx3 = getelementptr inbounds float, ptr %d, i64 182 store float %1, ptr %arrayidx3, align 483 ret void84 85; CHECK-LABEL: @test3sp86; CHECK-DAG: fmr [[F1:[0-9]+]], 187; CHECK-DAG: li [[C1:[0-9]+]], 1288; CHECK-DAG: li [[C2:[0-9]+]], 889; CHECK-DAG: li [[C3:[0-9]+]], 490; CHECK-DAG: xsmaddmsp 4, 2, 191; CHECK-DAG: xsmaddasp 1, 2, 592 93; Note: We could convert this next FMA to M-type as well, but it would require94; re-ordering the instructions.95; CHECK-DAG: xsmaddasp [[F1]], 2, 396 97; CHECK-DAG: xsmaddmsp 3, 2, 498; CHECK-DAG: stxsspx [[F1]], 0, 899; CHECK-DAG: stxsspx 3, 8, [[C1]]100; CHECK-DAG: stxsspx 1, 8, [[C2]]101; CHECK-DAG: stxsspx 4, 8, [[C3]]102; CHECK: blr103 104; CHECK-FISL-LABEL: @test3sp105; CHECK-FISL-DAG: fmr [[F1:[0-9]+]], 1106; CHECK-FISL-DAG: xsmaddasp [[F1]], 2, 4107; CHECK-FISL-DAG: fmr 4, [[F1]]108; CHECK-FISL-DAG: xsmaddasp 4, 2, 3109; CHECK-FISL-DAG: li [[C1:[0-9]+]], 12110; CHECK-FISL-DAG: stxsspx 4, 8, [[C1]]111; CHECK-FISL-DAG: xsmaddasp 1, 2, 5112; CHECK-FISL-DAG: li [[C2:[0-9]+]], 8113; CHECK-FISL-DAG: stxsspx 1, 8, [[C2]]114; CHECK-FISL-DAG: li [[C3:[0-9]+]], 4115; CHECK-FISL-DAG: stxsspx 0, 8, [[C3]]116; CHECK-FISL: blr117}118 119define void @test4sp(float %a, float %b, float %c, float %e, float %f, ptr nocapture %d) #0 {120entry:121 %0 = tail call float @llvm.fma.f32(float %b, float %c, float %a)122 store float %0, ptr %d, align 4123 %1 = tail call float @llvm.fma.f32(float %b, float %e, float %a)124 %arrayidx1 = getelementptr inbounds float, ptr %d, i64 1125 store float %1, ptr %arrayidx1, align 4126 %2 = tail call float @llvm.fma.f32(float %b, float %c, float %1)127 %arrayidx3 = getelementptr inbounds float, ptr %d, i64 3128 store float %2, ptr %arrayidx3, align 4129 %3 = tail call float @llvm.fma.f32(float %b, float %f, float %a)130 %arrayidx4 = getelementptr inbounds float, ptr %d, i64 2131 store float %3, ptr %arrayidx4, align 4132 ret void133 134; CHECK-LABEL: @test4sp135; CHECK-DAG: fmr [[F1:[0-9]+]], 1136; CHECK-DAG: li [[C1:[0-9]+]], 4137; CHECK-DAG: li [[C2:[0-9]+]], 8138; CHECK-DAG: xsmaddmsp 4, 2, 1139 140; Note: We could convert this next FMA to M-type as well, but it would require141; re-ordering the instructions.142; CHECK-DAG: xsmaddasp 1, 2, 5143 144; CHECK-DAG: xsmaddasp [[F1]], 2, 3145; CHECK-DAG: stxsspx [[F1]], 0, 8146; CHECK-DAG: stxsspx 4, 8, [[C1]]147; CHECK-DAG: li [[C3:[0-9]+]], 12148; CHECK-DAG: xsmaddasp 4, 2, 3149; CHECK-DAG: stxsspx 4, 8, [[C3]]150; CHECK-DAG: stxsspx 1, 8, [[C2]]151; CHECK: blr152 153; CHECK-FISL-LABEL: @test4sp154; CHECK-FISL-DAG: fmr [[F1:[0-9]+]], 1155; CHECK-FISL-DAG: xsmaddasp [[F1]], 2, 3156; CHECK-FISL-DAG: stxsspx 0, 0, 8157; CHECK-FISL-DAG: fmr [[F1]], 1158; CHECK-FISL-DAG: xsmaddasp [[F1]], 2, 4159; CHECK-FISL-DAG: li [[C3:[0-9]+]], 4160; CHECK-FISL-DAG: stxsspx 0, 8, [[C3]]161; CHECK-FISL-DAG: xsmaddasp 0, 2, 3162; CHECK-FISL-DAG: li [[C1:[0-9]+]], 12163; CHECK-FISL-DAG: stxsspx 0, 8, [[C1]]164; CHECK-FISL-DAG: xsmaddasp 1, 2, 5165; CHECK-FISL-DAG: li [[C2:[0-9]+]], 8166; CHECK-FISL-DAG: stxsspx 1, 8, [[C2]]167; CHECK-FISL: blr168}169 170declare float @llvm.fma.f32(float, float, float) #0171