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1; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+vsx -O2 \2; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s3 4; RUN: llc -verify-machineinstrs -mcpu=pwr9 -O2 \5; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s \6; RUN: --check-prefix=CHECK-P9UP7 8; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=-power9-vector -O2 \9; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s10 11; RUN: llc -verify-machineinstrs -mcpu=pwr10 -O2 \12; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s \13; RUN: --check-prefix=CHECK-P9UP14 15@vf = global <4 x float> <float -1.500000e+00, float 2.500000e+00, float -3.500000e+00, float 4.500000e+00>, align 1616@vd = global <2 x double> <double 3.500000e+00, double -7.500000e+00>, align 1617@vsi = global <4 x i32> <i32 -1, i32 2, i32 -3, i32 4>, align 1618@vui = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 1619@vsll = global <2 x i64> <i64 255, i64 -937>, align 1620@vull = global <2 x i64> <i64 1447, i64 2894>, align 1621@res_vsi = common global <4 x i32> zeroinitializer, align 1622@res_vui = common global <4 x i32> zeroinitializer, align 1623@res_vf = common global <4 x float> zeroinitializer, align 1624@res_vsll = common global <2 x i64> zeroinitializer, align 1625@res_vull = common global <2 x i64> zeroinitializer, align 1626@res_vd = common global <2 x double> zeroinitializer, align 1627 28define void @test1() {29entry:30; CHECK-LABEL: test131; CHECK-P9UP-LABEL: test132; CHECK: lxvd2x33; CHECK-P9UP-DAG: lxv34 %0 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(ptr @vsi)35; CHECK: stxvd2x36; CHECK-P9UP-DAG: stxv37 store <4 x i32> %0, ptr @res_vsi, align 1638; CHECK: lxvd2x39; CHECK-P9UP-DAG: lxv40 %1 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(ptr @vui)41; CHECK: stxvd2x42; CHECK-P9UP-DAG: stxv43 store <4 x i32> %1, ptr @res_vui, align 1644; CHECK: lxvd2x45; CHECK-P9UP-DAG: lxv46 %2 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(ptr @vf)47 %3 = bitcast <4 x i32> %2 to <4 x float>48; CHECK: stxvd2x49; CHECK-P9UP-DAG: stxv50 store <4 x float> %3, ptr @res_vf, align 1651; CHECK: lxvd2x52; CHECK-P9UP-DAG: lxv53 %4 = call <2 x double> @llvm.ppc.vsx.lxvd2x(ptr @vsll)54 %5 = bitcast <2 x double> %4 to <2 x i64>55; CHECK: stxvd2x56; CHECK-P9UP-DAG: stxv57 store <2 x i64> %5, ptr @res_vsll, align 1658; CHECK: lxvd2x59; CHECK-P9UP-DAG: lxv60 %6 = call <2 x double> @llvm.ppc.vsx.lxvd2x(ptr @vull)61 %7 = bitcast <2 x double> %6 to <2 x i64>62; CHECK: stxvd2x63; CHECK-P9UP-DAG: stxv64 store <2 x i64> %7, ptr @res_vull, align 1665; CHECK: lxvd2x66; CHECK-P9UP-DAG: lxv67 %8 = call <2 x double> @llvm.ppc.vsx.lxvd2x(ptr @vd)68; CHECK: stxvd2x69; CHECK-P9UP-DAG: stxv70 store <2 x double> %8, ptr @res_vd, align 1671; CHECK: lxvd2x72; CHECK-P9UP-DAG: lxv73 %9 = load <4 x i32>, ptr @vsi, align 1674; CHECK: stxvd2x75; CHECK-P9UP-DAG: stxv76 call void @llvm.ppc.vsx.stxvw4x(<4 x i32> %9, ptr @res_vsi)77; CHECK: lxvd2x78; CHECK-P9UP-DAG: lxv79 %10 = load <4 x i32>, ptr @vui, align 1680; CHECK: stxvd2x81; CHECK-P9UP-DAG: stxv82 call void @llvm.ppc.vsx.stxvw4x(<4 x i32> %10, ptr @res_vui)83; CHECK: lxvd2x84; CHECK-P9UP-DAG: lxv85 %11 = load <4 x float>, ptr @vf, align 1686 %12 = bitcast <4 x float> %11 to <4 x i32>87; CHECK: stxvd2x88; CHECK-P9UP-DAG: stxv89 call void @llvm.ppc.vsx.stxvw4x(<4 x i32> %12, ptr @res_vf)90; CHECK: lxvd2x91; CHECK-P9UP-DAG: lxv92 %13 = load <2 x i64>, ptr @vsll, align 1693 %14 = bitcast <2 x i64> %13 to <2 x double>94; CHECK: stxvd2x95; CHECK-P9UP-DAG: stxv96 call void @llvm.ppc.vsx.stxvd2x(<2 x double> %14, ptr @res_vsll)97; CHECK: lxvd2x98; CHECK-P9UP-DAG: lxv99 %15 = load <2 x i64>, ptr @vull, align 16100 %16 = bitcast <2 x i64> %15 to <2 x double>101; CHECK: stxvd2x102; CHECK-P9UP-DAG: stxv103 call void @llvm.ppc.vsx.stxvd2x(<2 x double> %16, ptr @res_vull)104; CHECK: lxvd2x105; CHECK-P9UP-DAG: lxv106 %17 = load <2 x double>, ptr @vd, align 16107; CHECK: stxvd2x108; CHECK-P9UP-DAG: stxv109 call void @llvm.ppc.vsx.stxvd2x(<2 x double> %17, ptr @res_vd)110 ret void111}112 113declare void @llvm.ppc.vsx.stxvd2x(<2 x double>, ptr)114declare void @llvm.ppc.vsx.stxvw4x(<4 x i32>, ptr)115declare <2 x double> @llvm.ppc.vsx.lxvd2x(ptr)116declare <4 x i32> @llvm.ppc.vsx.lxvw4x(ptr)117