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1; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+vsx -O2 \2; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s > %t3; RUN: grep lxvw4x < %t | count 34; RUN: grep lxvd2x < %t | count 35; RUN: grep stxvw4x < %t | count 36; RUN: grep stxvd2x < %t | count 37 8; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+vsx -O0 -fast-isel=1 \9; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s > %t10; RUN: grep lxvw4x < %t | count 311; RUN: grep lxvd2x < %t | count 312; RUN: grep stxvw4x < %t | count 313; RUN: grep stxvd2x < %t | count 314 15; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+vsx -O2 \16; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s > %t17; RUN: grep lxvd2x < %t | count 618; RUN: grep stxvd2x < %t | count 619 20; RUN: llc -verify-machineinstrs -mcpu=pwr9 -O2 \21; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s > %t22; RUN: grep lxv < %t | count 623; RUN: grep stxv < %t | count 624 25 26@vsi = global <4 x i32> <i32 -1, i32 2, i32 -3, i32 4>, align 1627@vui = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 1628@vf = global <4 x float> <float -1.500000e+00, float 2.500000e+00, float -3.500000e+00, float 4.500000e+00>, align 1629@vsll = global <2 x i64> <i64 255, i64 -937>, align 1630@vull = global <2 x i64> <i64 1447, i64 2894>, align 1631@vd = global <2 x double> <double 3.500000e+00, double -7.500000e+00>, align 1632@res_vsi = common global <4 x i32> zeroinitializer, align 1633@res_vui = common global <4 x i32> zeroinitializer, align 1634@res_vf = common global <4 x float> zeroinitializer, align 1635@res_vsll = common global <2 x i64> zeroinitializer, align 1636@res_vull = common global <2 x i64> zeroinitializer, align 1637@res_vd = common global <2 x double> zeroinitializer, align 1638 39; Function Attrs: nounwind40define void @test1() {41entry:42 %0 = load <4 x i32>, ptr @vsi, align 1643 %1 = load <4 x i32>, ptr @vui, align 1644 %2 = load <4 x i32>, ptr @vf, align 1645 %3 = load <2 x double>, ptr @vsll, align 1646 %4 = load <2 x double>, ptr @vull, align 1647 %5 = load <2 x double>, ptr @vd, align 1648 store <4 x i32> %0, ptr @res_vsi, align 1649 store <4 x i32> %1, ptr @res_vui, align 1650 store <4 x i32> %2, ptr @res_vf, align 1651 store <2 x double> %3, ptr @res_vsll, align 1652 store <2 x double> %4, ptr @res_vull, align 1653 store <2 x double> %5, ptr @res_vd, align 1654 ret void55}56