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1; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+power8-vector < %s | FileCheck %s2; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+power8-vector < %s | FileCheck -check-prefix=CHECK-REG %s3; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+power8-vector -fast-isel -O0 < %s | FileCheck %s4; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+power8-vector -fast-isel -O0 < %s | FileCheck -check-prefix=CHECK-FISL %s5target datalayout = "E-m:e-i64:64-n32:64"6target triple = "powerpc64-unknown-linux-gnu"7 8; Unaligned loads/stores on P8 and later should use VSX where possible.9 10define <2 x double> @test28u(ptr %a) {11 %v = load <2 x double>, ptr %a, align 812 ret <2 x double> %v13 14; CHECK-LABEL: @test28u15; CHECK: lxvd2x 34, 0, 316; CHECK: blr17}18 19define void @test29u(ptr %a, <2 x double> %b) {20 store <2 x double> %b, ptr %a, align 821 ret void22 23; CHECK-LABEL: @test29u24; CHECK: stxvd2x 34, 0, 325; CHECK: blr26}27 28define <4 x float> @test32u(ptr %a) {29 %v = load <4 x float>, ptr %a, align 830 ret <4 x float> %v31 32; CHECK-REG-LABEL: @test32u33; CHECK-REG: lxvw4x 34, 0, 334; CHECK-REG: blr35 36; CHECK-FISL-LABEL: @test32u37; CHECK-FISL: lxvw4x 34, 0, 338; CHECK-FISL: blr39}40 41define void @test33u(ptr %a, <4 x float> %b) {42 store <4 x float> %b, ptr %a, align 843 ret void44 45; CHECK-REG-LABEL: @test33u46; CHECK-REG: stxvw4x 34, 0, 347; CHECK-REG: blr48 49; CHECK-FISL-LABEL: @test33u50; CHECK-FISL: stxvw4x 34, 0, 351; CHECK-FISL: blr52}53 54