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1; RUN: llc -verify-machineinstrs -mcpu=pwr9 \2; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s3 4; RUN: llc -verify-machineinstrs -mcpu=pwr9 \5; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s6 7@uca = global <16 x i8> zeroinitializer, align 168@ucb = global <16 x i8> zeroinitializer, align 169@sca = global <16 x i8> zeroinitializer, align 1610@scb = global <16 x i8> zeroinitializer, align 1611@usa = global <8 x i16> zeroinitializer, align 1612@usb = global <8 x i16> zeroinitializer, align 1613@ssa = global <8 x i16> zeroinitializer, align 1614@ssb = global <8 x i16> zeroinitializer, align 1615@uia = global <4 x i32> zeroinitializer, align 1616@uib = global <4 x i32> zeroinitializer, align 1617@sia = global <4 x i32> zeroinitializer, align 1618@sib = global <4 x i32> zeroinitializer, align 1619@ulla = global <2 x i64> zeroinitializer, align 1620@ullb = global <2 x i64> zeroinitializer, align 1621@slla = global <2 x i64> zeroinitializer, align 1622@sllb = global <2 x i64> zeroinitializer, align 1623@uxa = global <1 x i128> zeroinitializer, align 1624@uxb = global <1 x i128> zeroinitializer, align 1625@sxa = global <1 x i128> zeroinitializer, align 1626@sxb = global <1 x i128> zeroinitializer, align 1627@vfa = global <4 x float> zeroinitializer, align 1628@vfb = global <4 x float> zeroinitializer, align 1629@vda = global <2 x double> zeroinitializer, align 1630@vdb = global <2 x double> zeroinitializer, align 1631 32define void @_Z4testv() {33entry:34; CHECK-LABEL: @_Z4testv35 %0 = load <16 x i8>, ptr @uca, align 1636 %1 = load <16 x i8>, ptr @ucb, align 1637 %add.i = add <16 x i8> %1, %038 tail call void (...) @sink(<16 x i8> %add.i)39; CHECK: lxv 34, 0(3)40; CHECK: lxv 35, 0(3)41; CHECK: vaddubm 2, 3, 242; CHECK: stxv 34,43; CHECK: bl sink44 %2 = load <16 x i8>, ptr @sca, align 1645 %3 = load <16 x i8>, ptr @scb, align 1646 %add.i22 = add <16 x i8> %3, %247 tail call void (...) @sink(<16 x i8> %add.i22)48; CHECK: lxv 34, 0(3)49; CHECK: lxv 35, 0(3)50; CHECK: vaddubm 2, 3, 251; CHECK: stxv 34,52; CHECK: bl sink53 %4 = load <8 x i16>, ptr @usa, align 1654 %5 = load <8 x i16>, ptr @usb, align 1655 %add.i21 = add <8 x i16> %5, %456 tail call void (...) @sink(<8 x i16> %add.i21)57; CHECK: lxv 34, 0(3)58; CHECK: lxv 35, 0(3)59; CHECK: vadduhm 2, 3, 260; CHECK: stxv 34,61; CHECK: bl sink62 %6 = load <8 x i16>, ptr @ssa, align 1663 %7 = load <8 x i16>, ptr @ssb, align 1664 %add.i20 = add <8 x i16> %7, %665 tail call void (...) @sink(<8 x i16> %add.i20)66; CHECK: lxv 34, 0(3)67; CHECK: lxv 35, 0(3)68; CHECK: vadduhm 2, 3, 269; CHECK: stxv 34,70; CHECK: bl sink71 %8 = load <4 x i32>, ptr @uia, align 1672 %9 = load <4 x i32>, ptr @uib, align 1673 %add.i19 = add <4 x i32> %9, %874 tail call void (...) @sink(<4 x i32> %add.i19)75; CHECK: lxv 34, 0(3)76; CHECK: lxv 35, 0(3)77; CHECK: vadduwm 2, 3, 278; CHECK: stxv 34,79; CHECK: bl sink80 %10 = load <4 x i32>, ptr @sia, align 1681 %11 = load <4 x i32>, ptr @sib, align 1682 %add.i18 = add <4 x i32> %11, %1083 tail call void (...) @sink(<4 x i32> %add.i18)84; CHECK: lxv 34, 0(3)85; CHECK: lxv 35, 0(3)86; CHECK: vadduwm 2, 3, 287; CHECK: stxv 34,88; CHECK: bl sink89 %12 = load <2 x i64>, ptr @ulla, align 1690 %13 = load <2 x i64>, ptr @ullb, align 1691 %add.i17 = add <2 x i64> %13, %1292 tail call void (...) @sink(<2 x i64> %add.i17)93; CHECK: lxv 34, 0(3)94; CHECK: lxv 35, 0(3)95; CHECK: vaddudm 2, 3, 296; CHECK: stxv 34,97; CHECK: bl sink98 %14 = load <2 x i64>, ptr @slla, align 1699 %15 = load <2 x i64>, ptr @sllb, align 16100 %add.i16 = add <2 x i64> %15, %14101 tail call void (...) @sink(<2 x i64> %add.i16)102; CHECK: lxv 34, 0(3)103; CHECK: lxv 35, 0(3)104; CHECK: vaddudm 2, 3, 2105; CHECK: stxv 34,106; CHECK: bl sink107 %16 = load <1 x i128>, ptr @uxa, align 16108 %17 = load <1 x i128>, ptr @uxb, align 16109 %add.i15 = add <1 x i128> %17, %16110 tail call void (...) @sink(<1 x i128> %add.i15)111; CHECK: lxv 34, 0(3)112; CHECK: lxv 35, 0(3)113; CHECK: vadduqm 2, 3, 2114; CHECK: stxv 34,115; CHECK: bl sink116 %18 = load <1 x i128>, ptr @sxa, align 16117 %19 = load <1 x i128>, ptr @sxb, align 16118 %add.i14 = add <1 x i128> %19, %18119 tail call void (...) @sink(<1 x i128> %add.i14)120; CHECK: lxv 34, 0(3)121; CHECK: lxv 35, 0(3)122; CHECK: vadduqm 2, 3, 2123; CHECK: stxv 34,124; CHECK: bl sink125 %20 = load <4 x float>, ptr @vfa, align 16126 %21 = load <4 x float>, ptr @vfb, align 16127 %add.i13 = fadd <4 x float> %20, %21128 tail call void (...) @sink(<4 x float> %add.i13)129; CHECK: lxv 0, 0(3)130; CHECK: lxv 1, 0(3)131; CHECK: xvaddsp 34, 0, 1132; CHECK: stxv 34,133; CHECK: bl sink134 %22 = load <2 x double>, ptr @vda, align 16135 %23 = load <2 x double>, ptr @vdb, align 16136 %add.i12 = fadd <2 x double> %22, %23137 tail call void (...) @sink(<2 x double> %add.i12)138; CHECK: lxv 0, 0(3)139; CHECK: lxv 1, 0(3)140; CHECK: xvadddp 0, 0, 1141; CHECK: stxv 0,142; CHECK: bl sink143 ret void144}145 146; Function Attrs: nounwind readnone147define <4 x float> @testXVIEXPSP(<4 x i32> %a, <4 x i32> %b) {148entry:149 %0 = tail call <4 x float> @llvm.ppc.vsx.xviexpsp(<4 x i32> %a, <4 x i32> %b)150 ret <4 x float> %0151; CHECK-LABEL: testXVIEXPSP152; CHECK: xviexpsp 34, 34, 35153; CHECK: blr154}155; Function Attrs: nounwind readnone156declare <4 x float> @llvm.ppc.vsx.xviexpsp(<4 x i32>, <4 x i32>)157 158; Function Attrs: nounwind readnone159define <2 x double> @testXVIEXPDP(<2 x i64> %a, <2 x i64> %b) {160entry:161 %0 = tail call <2 x double> @llvm.ppc.vsx.xviexpdp(<2 x i64> %a, <2 x i64> %b)162 ret <2 x double> %0163; CHECK-LABEL: testXVIEXPDP164; CHECK: xviexpdp 34, 34, 35165; CHECK: blr166}167; Function Attrs: nounwind readnone168declare <2 x double> @llvm.ppc.vsx.xviexpdp(<2 x i64>, <2 x i64>)169 170define <16 x i8> @testVSLV(<16 x i8> %a, <16 x i8> %b) {171entry:172 %0 = tail call <16 x i8> @llvm.ppc.altivec.vslv(<16 x i8> %a, <16 x i8> %b)173 ret <16 x i8> %0174; CHECK-LABEL: testVSLV175; CHECK: vslv 2, 2, 3176; CHECK: blr177}178; Function Attrs: nounwind readnone179declare <16 x i8> @llvm.ppc.altivec.vslv(<16 x i8>, <16 x i8>)180 181; Function Attrs: nounwind readnone182define <16 x i8> @testVSRV(<16 x i8> %a, <16 x i8> %b) {183entry:184 %0 = tail call <16 x i8> @llvm.ppc.altivec.vsrv(<16 x i8> %a, <16 x i8> %b)185 ret <16 x i8> %0186; CHECK-LABEL: testVSRV187; CHECK: vsrv 2, 2, 3188; CHECK: blr189}190; Function Attrs: nounwind readnone191declare <16 x i8> @llvm.ppc.altivec.vsrv(<16 x i8>, <16 x i8>)192 193; Function Attrs: nounwind readnone194define <8 x i16> @testXVCVSPHP(<4 x float> %a) {195entry:196; CHECK-LABEL: testXVCVSPHP197; CHECK: xvcvsphp 34, 34198; CHECK: blr199 %0 = tail call <4 x float> @llvm.ppc.vsx.xvcvsphp(<4 x float> %a)200 %1 = bitcast <4 x float> %0 to <8 x i16>201 ret <8 x i16> %1202}203 204; Function Attrs: nounwind readnone205define <4 x i32> @testVRLWMI(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {206entry:207; CHECK-LABEL: testVRLWMI208; CHECK: vrlwmi 3, 2, 4209; CHECK: blr210 %0 = tail call <4 x i32> @llvm.ppc.altivec.vrlwmi(<4 x i32> %a, <4 x i32> %c, <4 x i32> %b)211 ret <4 x i32> %0212}213 214; Function Attrs: nounwind readnone215define <2 x i64> @testVRLDMI(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {216entry:217; CHECK-LABEL: testVRLDMI218; CHECK: vrldmi 3, 2, 4219; CHECK: blr220 %0 = tail call <2 x i64> @llvm.ppc.altivec.vrldmi(<2 x i64> %a, <2 x i64> %c, <2 x i64> %b)221 ret <2 x i64> %0222}223 224; Function Attrs: nounwind readnone225define <4 x i32> @testVRLWNM(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {226entry:227 %0 = tail call <4 x i32> @llvm.ppc.altivec.vrlwnm(<4 x i32> %a, <4 x i32> %b)228 %and.i = and <4 x i32> %0, %c229 ret <4 x i32> %and.i230; CHECK-LABEL: testVRLWNM231; CHECK: vrlwnm 2, 2, 3232; CHECK: xxland 34, 34, 36233; CHECK: blr234}235 236; Function Attrs: nounwind readnone237define <2 x i64> @testVRLDNM(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {238entry:239 %0 = tail call <2 x i64> @llvm.ppc.altivec.vrldnm(<2 x i64> %a, <2 x i64> %b)240 %and.i = and <2 x i64> %0, %c241 ret <2 x i64> %and.i242; CHECK-LABEL: testVRLDNM243; CHECK: vrldnm 2, 2, 3244; CHECK: xxland 34, 34, 36245; CHECK: blr246}247 248; Function Attrs: nounwind readnone249declare <4 x float> @llvm.ppc.vsx.xvcvsphp(<4 x float>)250 251; Function Attrs: nounwind readnone252declare <4 x i32> @llvm.ppc.altivec.vrlwmi(<4 x i32>, <4 x i32>, <4 x i32>)253 254; Function Attrs: nounwind readnone255declare <2 x i64> @llvm.ppc.altivec.vrldmi(<2 x i64>, <2 x i64>, <2 x i64>)256 257; Function Attrs: nounwind readnone258declare <4 x i32> @llvm.ppc.altivec.vrlwnm(<4 x i32>, <4 x i32>)259 260; Function Attrs: nounwind readnone261declare <2 x i64> @llvm.ppc.altivec.vrldnm(<2 x i64>, <2 x i64>)262 263define <4 x i32> @testXVXEXPSP(<4 x float> %a) {264entry:265 %0 = tail call <4 x i32> @llvm.ppc.vsx.xvxexpsp(<4 x float> %a)266 ret <4 x i32> %0267; CHECK-LABEL: testXVXEXPSP268; CHECK: xvxexpsp 34, 34269; CHECK: blr270}271; Function Attrs: nounwind readnone272declare <4 x i32> @llvm.ppc.vsx.xvxexpsp(<4 x float>)273 274; Function Attrs: nounwind readnone275define <2 x i64> @testXVXEXPDP(<2 x double> %a) {276entry:277 %0 = tail call <2 x i64> @llvm.ppc.vsx.xvxexpdp(<2 x double> %a)278 ret <2 x i64> %0279; CHECK-LABEL: testXVXEXPDP280; CHECK: xvxexpdp 34, 34281; CHECK: blr282}283; Function Attrs: nounwind readnone284declare <2 x i64>@llvm.ppc.vsx.xvxexpdp(<2 x double>)285 286; Function Attrs: nounwind readnone287define <4 x i32> @testXVXSIGSP(<4 x float> %a) {288entry:289 %0 = tail call <4 x i32> @llvm.ppc.vsx.xvxsigsp(<4 x float> %a)290 ret <4 x i32> %0291; CHECK-LABEL: testXVXSIGSP292; CHECK: xvxsigsp 34, 34293; CHECK: blr294}295; Function Attrs: nounwind readnone296declare <4 x i32> @llvm.ppc.vsx.xvxsigsp(<4 x float>)297 298; Function Attrs: nounwind readnone299define <2 x i64> @testXVXSIGDP(<2 x double> %a) {300entry:301 %0 = tail call <2 x i64> @llvm.ppc.vsx.xvxsigdp(<2 x double> %a)302 ret <2 x i64> %0303; CHECK-LABEL: testXVXSIGDP304; CHECK: xvxsigdp 34, 34305; CHECK: blr306}307; Function Attrs: nounwind readnone308declare <2 x i64> @llvm.ppc.vsx.xvxsigdp(<2 x double>)309 310; Function Attrs: nounwind readnone311define <4 x i32> @testXVTSTDCSP(<4 x float> %a) {312entry:313 %0 = tail call <4 x i32> @llvm.ppc.vsx.xvtstdcsp(<4 x float> %a, i32 127)314 ret <4 x i32> %0315; CHECK-LABEL: testXVTSTDCSP316; CHECK: xvtstdcsp 34, 34, 127317; CHECK: blr318}319; Function Attrs: nounwind readnone320declare <4 x i32> @llvm.ppc.vsx.xvtstdcsp(<4 x float> %a, i32 %b)321 322; Function Attrs: nounwind readnone323define <2 x i64> @testXVTSTDCDP(<2 x double> %a) {324entry:325 %0 = tail call <2 x i64> @llvm.ppc.vsx.xvtstdcdp(<2 x double> %a, i32 127)326 ret <2 x i64> %0327; CHECK-LABEL: testXVTSTDCDP328; CHECK: xvtstdcdp 34, 34, 127329; CHECK: blr330}331; Function Attrs: nounwind readnone332declare <2 x i64> @llvm.ppc.vsx.xvtstdcdp(<2 x double> %a, i32 %b)333 334define <4 x float> @testXVCVHPSP(<8 x i16> %a) {335entry:336 %0 = tail call <4 x float>@llvm.ppc.vsx.xvcvhpsp(<8 x i16> %a)337 ret <4 x float> %0338; CHECK-LABEL: testXVCVHPSP339; CHECK: xvcvhpsp 34, 34340; CHECK: blr341}342; Function Attrs: nounwind readnone343declare <4 x float>@llvm.ppc.vsx.xvcvhpsp(<8 x i16>)344 345; Function Attrs: nounwind readnone346define <4 x i32> @testLXVL(ptr %a, i64 %b) {347entry:348 %0 = tail call <4 x i32> @llvm.ppc.vsx.lxvl(ptr %a, i64 %b)349 ret <4 x i32> %0350; CHECK-LABEL: testLXVL351; CHECK: lxvl 34, 3, 4352; CHECK: blr353}354; Function Attrs: nounwind readnone355declare <4 x i32> @llvm.ppc.vsx.lxvl(ptr, i64)356 357define void @testSTXVL(<4 x i32> %a, ptr %b, i64 %c) {358entry:359 tail call void @llvm.ppc.vsx.stxvl(<4 x i32> %a, ptr %b, i64 %c)360 ret void361; CHECK-LABEL: testSTXVL362; CHECK: stxvl 34, 5, 6363; CHECK: blr364}365; Function Attrs: nounwind readnone366declare void @llvm.ppc.vsx.stxvl(<4 x i32>, ptr, i64)367 368; Function Attrs: nounwind readnone369define <4 x i32> @testLXVLL(ptr %a, i64 %b) {370entry:371 %0 = tail call <4 x i32> @llvm.ppc.vsx.lxvll(ptr %a, i64 %b)372 ret <4 x i32> %0373; CHECK-LABEL: testLXVLL374; CHECK: lxvll 34, 3, 4375; CHECK: blr376}377; Function Attrs: nounwind readnone378declare <4 x i32> @llvm.ppc.vsx.lxvll(ptr, i64)379 380define void @testSTXVLL(<4 x i32> %a, ptr %b, i64 %c) {381entry:382 tail call void @llvm.ppc.vsx.stxvll(<4 x i32> %a, ptr %b, i64 %c)383 ret void384; CHECK-LABEL: testSTXVLL385; CHECK: stxvll 34, 5, 6386; CHECK: blr387}388; Function Attrs: nounwind readnone389declare void @llvm.ppc.vsx.stxvll(<4 x i32>, ptr, i64)390 391define <4 x i32> @test0(<4 x i32> %a) local_unnamed_addr #0 {392entry:393 %sub.i = sub <4 x i32> zeroinitializer, %a394 ret <4 x i32> %sub.i395 396; CHECK-LABEL: @test0397; CHECK: vnegw 2, 2398; CHECK: blr399 400}401 402define <2 x i64> @test1(<2 x i64> %a) local_unnamed_addr #0 {403entry:404 %sub.i = sub <2 x i64> zeroinitializer, %a405 ret <2 x i64> %sub.i406 407; CHECK-LABEL: @test1408; CHECK: vnegd 2, 2409; CHECK: blr410 411}412 413declare void @sink(...)414 415; stack object should be accessed using D-form load/store instead of X-form416define signext i32 @func1() {417; CHECK-LABEL: @func1418; CHECK-NOT: stxvx419; CHECK: stxv {{[0-9]+}}, {{[0-9]+}}(1)420; CHECK-NOT: stxvx421; CHECK: blr422entry:423 %a = alloca [4 x i32], align 4424 call void @llvm.memset.p0.i64(ptr nonnull align 4 %a, i8 0, i64 16, i1 false)425 %call = call signext i32 @callee(ptr nonnull %a) #3426 ret i32 %call427}428 429; stack object should be accessed using D-form load/store instead of X-form430define signext i32 @func2() {431; CHECK-LABEL: @func2432; CHECK-NOT: stxvx433; CHECK: stxv [[ZEROREG:[0-9]+]], {{[0-9]+}}(1)434; CHECK: stxv [[ZEROREG]], {{[0-9]+}}(1)435; CHECK: stxv [[ZEROREG]], {{[0-9]+}}(1)436; CHECK: stxv [[ZEROREG]], {{[0-9]+}}(1)437; CHECK-NOT: stxvx438; CHECK: blr439entry:440 %a = alloca [16 x i32], align 4441 call void @llvm.memset.p0.i64(ptr nonnull align 4 %a, i8 0, i64 64, i1 false)442 %call = call signext i32 @callee(ptr nonnull %a) #3443 ret i32 %call444}445 446declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1) #1447declare signext i32 @callee(ptr) local_unnamed_addr #2448