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1; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx \2; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s3; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx \4; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck \5; RUN: -check-prefix=CHECK-REG %s6; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 \7; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s8; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 \9; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | \10; RUN: FileCheck -check-prefix=CHECK-FISL %s11; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr \12; RUN: -ppc-asm-full-reg-names < %s | FileCheck -check-prefix=CHECK-P9-REG %s13; RUN: llc -verify-machineinstrs -mcpu=pwr9 -fast-isel -O0 \14; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck \15; RUN: -check-prefix=CHECK-P9-FISL %s16target datalayout = "E-m:e-i64:64-n32:64"17target triple = "powerpc64-unknown-linux-gnu"18 19define double @foo1(double %a) nounwind {20entry:21 call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() nounwind22 br label %return23 24; CHECK-REG: @foo125; CHECK-REG: xxlor v2, f1, f126; CHECK-REG: xxlor f1, v2, v227; CHECK-REG: blr28 29; CHECK-FISL: @foo130; CHECK-FISL-NOT: lis31; CHECK-FISL-NOT: ori32; CHECK-FISL: li r3, -15233; CHECK-FISL-NOT: lis34; CHECK-FISL-NOT: ori35; CHECK-FISL: stxsdx f1, r1, r336; CHECK-FISL: blr37 38; CHECK-P9-REG: @foo139; CHECK-P9-REG: xscpsgndp v2, f1, f140; CHECK-P9-REG: xscpsgndp f1, v2, v241; CHECK-P9-REG: blr42 43; CHECK-P9-FISL: @foo144; CHECK-P9-FISL: stfd f31, -8(r1)45; CHECK-P9-FISL: blr46 47return: ; preds = %entry48 ret double %a49}50 51define double @foo2(double %a) nounwind {52entry:53 %b = fadd double %a, %a54 call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() nounwind55 br label %return56 57; CHECK-REG: @foo258; CHECK-REG: {{xxlor|xsadddp}} v2, f1, f159; CHECK-REG: {{xxlor|xsadddp}} f1, f0, f060; CHECK-REG: blr61 62; CHECK-FISL: @foo263; CHECK-FISL: xsadddp [[REG0:f[0-9]+]], f1, f164; CHECK-FISL: stxsdx [[REG0]], r1, r365; CHECK-FISL: lxsdx f1, r1, r366; CHECK-FISL: blr67 68; CHECK-P9-REG: @foo269; CHECK-P9-REG: {{xscpsgndp|xsadddp}} v2, f1, f170; CHECK-P9-REG: {{xscpsgndp|xsadddp}} f1, v2, v271; CHECK-P9-REG: blr72 73; CHECK-P9-FISL: @foo274; CHECK-P9-FISL: xsadddp [[REG0:f[0-9]+]], f1, f175; CHECK-P9-FISL: stfd [[REG0]], -152(r1)76; CHECK-P9-FISL: lfd f1, -152(r1)77; CHECK-P9-FISL: blr78 79return: ; preds = %entry80 ret double %b81}82 83define double @foo3(double %a) nounwind {84entry:85 call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31},~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"() nounwind86 br label %return87 88; CHECK: @foo389; CHECK: stxsdx f1, r1, r390; CHECK: lxsdx f0, r1, r391; CHECK: xsadddp f1, f0, f092; CHECK: blr93 94; CHECK-P9-REG-LABEL: foo395; CHECK-P9-REG: stdu r1, -400(r1)96; CHECK-P9-REG-DAG: lfd f30, 384(r1)97; CHECK-P9-REG-DAG: xsadddp f1, f0, f098 99; CHECK-P9-FISL-LABEL: foo3100; CHECK-P9-FISL: stdu r1, -400(r1)101; CHECK-P9-FISL: lfd f0, 56(r1)102; CHECK-P9-FISL: xsadddp f1, f0, f0103return: ; preds = %entry104 %b = fadd double %a, %a105 ret double %b106}107 108