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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 \3; RUN: -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx \4; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s5; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 \6; RUN: -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx \7; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck \8; RUN: -check-prefix=CHECK-REG %s9; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 \10; RUN: -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx -fast-isel -O0 \11; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck \12; RUN: -check-prefix=CHECK-FISL %s13; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr8 \14; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mattr=+vsx \15; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck \16; RUN: -check-prefix=CHECK-LE %s17 18define double @test1(double %a, double %b) {19; CHECK-LABEL: test1:20; CHECK: # %bb.0: # %entry21; CHECK-NEXT: xsmuldp f1, f1, f222; CHECK-NEXT: blr23;24; CHECK-REG-LABEL: test1:25; CHECK-REG: # %bb.0: # %entry26; CHECK-REG-NEXT: xsmuldp f1, f1, f227; CHECK-REG-NEXT: blr28;29; CHECK-FISL-LABEL: test1:30; CHECK-FISL: # %bb.0: # %entry31; CHECK-FISL-NEXT: xsmuldp f1, f1, f232; CHECK-FISL-NEXT: blr33;34; CHECK-LE-LABEL: test1:35; CHECK-LE: # %bb.0: # %entry36; CHECK-LE-NEXT: xsmuldp f1, f1, f237; CHECK-LE-NEXT: blr38entry:39 %v = fmul double %a, %b40 ret double %v41 42 43}44 45define double @test2(double %a, double %b) {46; CHECK-LABEL: test2:47; CHECK: # %bb.0: # %entry48; CHECK-NEXT: xsdivdp f1, f1, f249; CHECK-NEXT: blr50;51; CHECK-REG-LABEL: test2:52; CHECK-REG: # %bb.0: # %entry53; CHECK-REG-NEXT: xsdivdp f1, f1, f254; CHECK-REG-NEXT: blr55;56; CHECK-FISL-LABEL: test2:57; CHECK-FISL: # %bb.0: # %entry58; CHECK-FISL-NEXT: xsdivdp f1, f1, f259; CHECK-FISL-NEXT: blr60;61; CHECK-LE-LABEL: test2:62; CHECK-LE: # %bb.0: # %entry63; CHECK-LE-NEXT: xsdivdp f1, f1, f264; CHECK-LE-NEXT: blr65entry:66 %v = fdiv double %a, %b67 ret double %v68 69 70}71 72define double @test3(double %a, double %b) {73; CHECK-LABEL: test3:74; CHECK: # %bb.0: # %entry75; CHECK-NEXT: xsadddp f1, f1, f276; CHECK-NEXT: blr77;78; CHECK-REG-LABEL: test3:79; CHECK-REG: # %bb.0: # %entry80; CHECK-REG-NEXT: xsadddp f1, f1, f281; CHECK-REG-NEXT: blr82;83; CHECK-FISL-LABEL: test3:84; CHECK-FISL: # %bb.0: # %entry85; CHECK-FISL-NEXT: xsadddp f1, f1, f286; CHECK-FISL-NEXT: blr87;88; CHECK-LE-LABEL: test3:89; CHECK-LE: # %bb.0: # %entry90; CHECK-LE-NEXT: xsadddp f1, f1, f291; CHECK-LE-NEXT: blr92entry:93 %v = fadd double %a, %b94 ret double %v95 96 97}98 99define <2 x double> @test4(<2 x double> %a, <2 x double> %b) {100; CHECK-LABEL: test4:101; CHECK: # %bb.0: # %entry102; CHECK-NEXT: xvadddp v2, v2, v3103; CHECK-NEXT: blr104;105; CHECK-REG-LABEL: test4:106; CHECK-REG: # %bb.0: # %entry107; CHECK-REG-NEXT: xvadddp v2, v2, v3108; CHECK-REG-NEXT: blr109;110; CHECK-FISL-LABEL: test4:111; CHECK-FISL: # %bb.0: # %entry112; CHECK-FISL-NEXT: xvadddp v2, v2, v3113; CHECK-FISL-NEXT: blr114;115; CHECK-LE-LABEL: test4:116; CHECK-LE: # %bb.0: # %entry117; CHECK-LE-NEXT: xvadddp v2, v2, v3118; CHECK-LE-NEXT: blr119entry:120 %v = fadd <2 x double> %a, %b121 ret <2 x double> %v122 123 124}125 126define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b) {127; CHECK-LABEL: test5:128; CHECK: # %bb.0: # %entry129; CHECK-NEXT: xxlxor v2, v2, v3130; CHECK-NEXT: blr131;132; CHECK-REG-LABEL: test5:133; CHECK-REG: # %bb.0: # %entry134; CHECK-REG-NEXT: xxlxor v2, v2, v3135; CHECK-REG-NEXT: blr136;137; CHECK-FISL-LABEL: test5:138; CHECK-FISL: # %bb.0: # %entry139; CHECK-FISL-NEXT: xxlxor v2, v2, v3140; CHECK-FISL-NEXT: blr141;142; CHECK-LE-LABEL: test5:143; CHECK-LE: # %bb.0: # %entry144; CHECK-LE-NEXT: xxlxor v2, v2, v3145; CHECK-LE-NEXT: blr146entry:147 %v = xor <4 x i32> %a, %b148 ret <4 x i32> %v149 150 151 152}153 154define <8 x i16> @test6(<8 x i16> %a, <8 x i16> %b) {155; CHECK-LABEL: test6:156; CHECK: # %bb.0: # %entry157; CHECK-NEXT: xxlxor v2, v2, v3158; CHECK-NEXT: blr159;160; CHECK-REG-LABEL: test6:161; CHECK-REG: # %bb.0: # %entry162; CHECK-REG-NEXT: xxlxor v2, v2, v3163; CHECK-REG-NEXT: blr164;165; CHECK-FISL-LABEL: test6:166; CHECK-FISL: # %bb.0: # %entry167; CHECK-FISL-NEXT: xxlxor v2, v2, v3168; CHECK-FISL-NEXT: blr169;170; CHECK-LE-LABEL: test6:171; CHECK-LE: # %bb.0: # %entry172; CHECK-LE-NEXT: xxlxor v2, v2, v3173; CHECK-LE-NEXT: blr174entry:175 %v = xor <8 x i16> %a, %b176 ret <8 x i16> %v177 178 179 180}181 182define <16 x i8> @test7(<16 x i8> %a, <16 x i8> %b) {183; CHECK-LABEL: test7:184; CHECK: # %bb.0: # %entry185; CHECK-NEXT: xxlxor v2, v2, v3186; CHECK-NEXT: blr187;188; CHECK-REG-LABEL: test7:189; CHECK-REG: # %bb.0: # %entry190; CHECK-REG-NEXT: xxlxor v2, v2, v3191; CHECK-REG-NEXT: blr192;193; CHECK-FISL-LABEL: test7:194; CHECK-FISL: # %bb.0: # %entry195; CHECK-FISL-NEXT: xxlxor v2, v2, v3196; CHECK-FISL-NEXT: blr197;198; CHECK-LE-LABEL: test7:199; CHECK-LE: # %bb.0: # %entry200; CHECK-LE-NEXT: xxlxor v2, v2, v3201; CHECK-LE-NEXT: blr202entry:203 %v = xor <16 x i8> %a, %b204 ret <16 x i8> %v205 206 207 208}209 210define <4 x i32> @test8(<4 x i32> %a, <4 x i32> %b) {211; CHECK-LABEL: test8:212; CHECK: # %bb.0: # %entry213; CHECK-NEXT: xxlor v2, v2, v3214; CHECK-NEXT: blr215;216; CHECK-REG-LABEL: test8:217; CHECK-REG: # %bb.0: # %entry218; CHECK-REG-NEXT: xxlor v2, v2, v3219; CHECK-REG-NEXT: blr220;221; CHECK-FISL-LABEL: test8:222; CHECK-FISL: # %bb.0: # %entry223; CHECK-FISL-NEXT: xxlor v2, v2, v3224; CHECK-FISL-NEXT: blr225;226; CHECK-LE-LABEL: test8:227; CHECK-LE: # %bb.0: # %entry228; CHECK-LE-NEXT: xxlor v2, v2, v3229; CHECK-LE-NEXT: blr230entry:231 %v = or <4 x i32> %a, %b232 ret <4 x i32> %v233 234 235 236}237 238define <8 x i16> @test9(<8 x i16> %a, <8 x i16> %b) {239; CHECK-LABEL: test9:240; CHECK: # %bb.0: # %entry241; CHECK-NEXT: xxlor v2, v2, v3242; CHECK-NEXT: blr243;244; CHECK-REG-LABEL: test9:245; CHECK-REG: # %bb.0: # %entry246; CHECK-REG-NEXT: xxlor v2, v2, v3247; CHECK-REG-NEXT: blr248;249; CHECK-FISL-LABEL: test9:250; CHECK-FISL: # %bb.0: # %entry251; CHECK-FISL-NEXT: xxlor v2, v2, v3252; CHECK-FISL-NEXT: blr253;254; CHECK-LE-LABEL: test9:255; CHECK-LE: # %bb.0: # %entry256; CHECK-LE-NEXT: xxlor v2, v2, v3257; CHECK-LE-NEXT: blr258entry:259 %v = or <8 x i16> %a, %b260 ret <8 x i16> %v261 262 263 264}265 266define <16 x i8> @test10(<16 x i8> %a, <16 x i8> %b) {267; CHECK-LABEL: test10:268; CHECK: # %bb.0: # %entry269; CHECK-NEXT: xxlor v2, v2, v3270; CHECK-NEXT: blr271;272; CHECK-REG-LABEL: test10:273; CHECK-REG: # %bb.0: # %entry274; CHECK-REG-NEXT: xxlor v2, v2, v3275; CHECK-REG-NEXT: blr276;277; CHECK-FISL-LABEL: test10:278; CHECK-FISL: # %bb.0: # %entry279; CHECK-FISL-NEXT: xxlor v2, v2, v3280; CHECK-FISL-NEXT: blr281;282; CHECK-LE-LABEL: test10:283; CHECK-LE: # %bb.0: # %entry284; CHECK-LE-NEXT: xxlor v2, v2, v3285; CHECK-LE-NEXT: blr286entry:287 %v = or <16 x i8> %a, %b288 ret <16 x i8> %v289 290 291 292}293 294define <4 x i32> @test11(<4 x i32> %a, <4 x i32> %b) {295; CHECK-LABEL: test11:296; CHECK: # %bb.0: # %entry297; CHECK-NEXT: xxland v2, v2, v3298; CHECK-NEXT: blr299;300; CHECK-REG-LABEL: test11:301; CHECK-REG: # %bb.0: # %entry302; CHECK-REG-NEXT: xxland v2, v2, v3303; CHECK-REG-NEXT: blr304;305; CHECK-FISL-LABEL: test11:306; CHECK-FISL: # %bb.0: # %entry307; CHECK-FISL-NEXT: xxland v2, v2, v3308; CHECK-FISL-NEXT: blr309;310; CHECK-LE-LABEL: test11:311; CHECK-LE: # %bb.0: # %entry312; CHECK-LE-NEXT: xxland v2, v2, v3313; CHECK-LE-NEXT: blr314entry:315 %v = and <4 x i32> %a, %b316 ret <4 x i32> %v317 318 319 320}321 322define <8 x i16> @test12(<8 x i16> %a, <8 x i16> %b) {323; CHECK-LABEL: test12:324; CHECK: # %bb.0: # %entry325; CHECK-NEXT: xxland v2, v2, v3326; CHECK-NEXT: blr327;328; CHECK-REG-LABEL: test12:329; CHECK-REG: # %bb.0: # %entry330; CHECK-REG-NEXT: xxland v2, v2, v3331; CHECK-REG-NEXT: blr332;333; CHECK-FISL-LABEL: test12:334; CHECK-FISL: # %bb.0: # %entry335; CHECK-FISL-NEXT: xxland v2, v2, v3336; CHECK-FISL-NEXT: blr337;338; CHECK-LE-LABEL: test12:339; CHECK-LE: # %bb.0: # %entry340; CHECK-LE-NEXT: xxland v2, v2, v3341; CHECK-LE-NEXT: blr342entry:343 %v = and <8 x i16> %a, %b344 ret <8 x i16> %v345 346 347 348}349 350define <16 x i8> @test13(<16 x i8> %a, <16 x i8> %b) {351; CHECK-LABEL: test13:352; CHECK: # %bb.0: # %entry353; CHECK-NEXT: xxland v2, v2, v3354; CHECK-NEXT: blr355;356; CHECK-REG-LABEL: test13:357; CHECK-REG: # %bb.0: # %entry358; CHECK-REG-NEXT: xxland v2, v2, v3359; CHECK-REG-NEXT: blr360;361; CHECK-FISL-LABEL: test13:362; CHECK-FISL: # %bb.0: # %entry363; CHECK-FISL-NEXT: xxland v2, v2, v3364; CHECK-FISL-NEXT: blr365;366; CHECK-LE-LABEL: test13:367; CHECK-LE: # %bb.0: # %entry368; CHECK-LE-NEXT: xxland v2, v2, v3369; CHECK-LE-NEXT: blr370entry:371 %v = and <16 x i8> %a, %b372 ret <16 x i8> %v373 374 375 376}377 378define <4 x i32> @test14(<4 x i32> %a, <4 x i32> %b) {379; CHECK-LABEL: test14:380; CHECK: # %bb.0: # %entry381; CHECK-NEXT: xxlnor v2, v2, v3382; CHECK-NEXT: blr383;384; CHECK-REG-LABEL: test14:385; CHECK-REG: # %bb.0: # %entry386; CHECK-REG-NEXT: xxlnor v2, v2, v3387; CHECK-REG-NEXT: blr388;389; CHECK-FISL-LABEL: test14:390; CHECK-FISL: # %bb.0: # %entry391; CHECK-FISL-NEXT: xxlor vs0, v2, v3392; CHECK-FISL-NEXT: xxlnor v2, v2, v3393; CHECK-FISL-NEXT: blr394;395; CHECK-LE-LABEL: test14:396; CHECK-LE: # %bb.0: # %entry397; CHECK-LE-NEXT: xxlnor v2, v2, v3398; CHECK-LE-NEXT: blr399entry:400 %v = or <4 x i32> %a, %b401 %w = xor <4 x i32> %v, <i32 -1, i32 -1, i32 -1, i32 -1>402 ret <4 x i32> %w403 404 405 406}407 408define <8 x i16> @test15(<8 x i16> %a, <8 x i16> %b) {409; CHECK-LABEL: test15:410; CHECK: # %bb.0: # %entry411; CHECK-NEXT: xxlnor v2, v2, v3412; CHECK-NEXT: blr413;414; CHECK-REG-LABEL: test15:415; CHECK-REG: # %bb.0: # %entry416; CHECK-REG-NEXT: xxlnor v2, v2, v3417; CHECK-REG-NEXT: blr418;419; CHECK-FISL-LABEL: test15:420; CHECK-FISL: # %bb.0: # %entry421; CHECK-FISL-NEXT: xxlor v4, v2, v3422; CHECK-FISL-NEXT: xxlnor v2, v2, v3423; CHECK-FISL-NEXT: blr424;425; CHECK-LE-LABEL: test15:426; CHECK-LE: # %bb.0: # %entry427; CHECK-LE-NEXT: xxlnor v2, v2, v3428; CHECK-LE-NEXT: blr429entry:430 %v = or <8 x i16> %a, %b431 %w = xor <8 x i16> %v, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>432 ret <8 x i16> %w433 434 435 436}437 438define <16 x i8> @test16(<16 x i8> %a, <16 x i8> %b) {439; CHECK-LABEL: test16:440; CHECK: # %bb.0: # %entry441; CHECK-NEXT: xxlnor v2, v2, v3442; CHECK-NEXT: blr443;444; CHECK-REG-LABEL: test16:445; CHECK-REG: # %bb.0: # %entry446; CHECK-REG-NEXT: xxlnor v2, v2, v3447; CHECK-REG-NEXT: blr448;449; CHECK-FISL-LABEL: test16:450; CHECK-FISL: # %bb.0: # %entry451; CHECK-FISL-NEXT: xxlor v4, v2, v3452; CHECK-FISL-NEXT: xxlnor v2, v2, v3453; CHECK-FISL-NEXT: blr454;455; CHECK-LE-LABEL: test16:456; CHECK-LE: # %bb.0: # %entry457; CHECK-LE-NEXT: xxlnor v2, v2, v3458; CHECK-LE-NEXT: blr459entry:460 %v = or <16 x i8> %a, %b461 %w = xor <16 x i8> %v, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>462 ret <16 x i8> %w463 464 465 466}467 468define <4 x i32> @test17(<4 x i32> %a, <4 x i32> %b) {469; CHECK-LABEL: test17:470; CHECK: # %bb.0: # %entry471; CHECK-NEXT: xxlandc v2, v2, v3472; CHECK-NEXT: blr473;474; CHECK-REG-LABEL: test17:475; CHECK-REG: # %bb.0: # %entry476; CHECK-REG-NEXT: xxlandc v2, v2, v3477; CHECK-REG-NEXT: blr478;479; CHECK-FISL-LABEL: test17:480; CHECK-FISL: # %bb.0: # %entry481; CHECK-FISL-NEXT: xxlnor vs0, v3, v3482; CHECK-FISL-NEXT: xxland v2, v2, vs0483; CHECK-FISL-NEXT: blr484;485; CHECK-LE-LABEL: test17:486; CHECK-LE: # %bb.0: # %entry487; CHECK-LE-NEXT: xxlandc v2, v2, v3488; CHECK-LE-NEXT: blr489entry:490 %w = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>491 %v = and <4 x i32> %a, %w492 ret <4 x i32> %v493 494 495 496}497 498define <8 x i16> @test18(<8 x i16> %a, <8 x i16> %b) {499; CHECK-LABEL: test18:500; CHECK: # %bb.0: # %entry501; CHECK-NEXT: xxlandc v2, v2, v3502; CHECK-NEXT: blr503;504; CHECK-REG-LABEL: test18:505; CHECK-REG: # %bb.0: # %entry506; CHECK-REG-NEXT: xxlandc v2, v2, v3507; CHECK-REG-NEXT: blr508;509; CHECK-FISL-LABEL: test18:510; CHECK-FISL: # %bb.0: # %entry511; CHECK-FISL-NEXT: xxlnor v4, v3, v3512; CHECK-FISL-NEXT: xxlandc v2, v2, v3513; CHECK-FISL-NEXT: blr514;515; CHECK-LE-LABEL: test18:516; CHECK-LE: # %bb.0: # %entry517; CHECK-LE-NEXT: xxlandc v2, v2, v3518; CHECK-LE-NEXT: blr519entry:520 %w = xor <8 x i16> %b, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>521 %v = and <8 x i16> %a, %w522 ret <8 x i16> %v523 524 525 526}527 528define <16 x i8> @test19(<16 x i8> %a, <16 x i8> %b) {529; CHECK-LABEL: test19:530; CHECK: # %bb.0: # %entry531; CHECK-NEXT: xxlandc v2, v2, v3532; CHECK-NEXT: blr533;534; CHECK-REG-LABEL: test19:535; CHECK-REG: # %bb.0: # %entry536; CHECK-REG-NEXT: xxlandc v2, v2, v3537; CHECK-REG-NEXT: blr538;539; CHECK-FISL-LABEL: test19:540; CHECK-FISL: # %bb.0: # %entry541; CHECK-FISL-NEXT: xxlnor v4, v3, v3542; CHECK-FISL-NEXT: xxlandc v2, v2, v3543; CHECK-FISL-NEXT: blr544;545; CHECK-LE-LABEL: test19:546; CHECK-LE: # %bb.0: # %entry547; CHECK-LE-NEXT: xxlandc v2, v2, v3548; CHECK-LE-NEXT: blr549entry:550 %w = xor <16 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>551 %v = and <16 x i8> %a, %w552 ret <16 x i8> %v553 554 555 556}557 558define <4 x i32> @test20(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {559; CHECK-LABEL: test20:560; CHECK: # %bb.0: # %entry561; CHECK-NEXT: vcmpequw v4, v4, v5562; CHECK-NEXT: xxsel v2, v3, v2, v4563; CHECK-NEXT: blr564;565; CHECK-REG-LABEL: test20:566; CHECK-REG: # %bb.0: # %entry567; CHECK-REG-NEXT: vcmpequw v4, v4, v5568; CHECK-REG-NEXT: xxsel v2, v3, v2, v4569; CHECK-REG-NEXT: blr570;571; CHECK-FISL-LABEL: test20:572; CHECK-FISL: # %bb.0: # %entry573; CHECK-FISL-NEXT: vcmpequw v4, v4, v5574; CHECK-FISL-NEXT: xxsel v2, v3, v2, v4575; CHECK-FISL-NEXT: blr576;577; CHECK-LE-LABEL: test20:578; CHECK-LE: # %bb.0: # %entry579; CHECK-LE-NEXT: vcmpequw v4, v4, v5580; CHECK-LE-NEXT: xxsel v2, v3, v2, v4581; CHECK-LE-NEXT: blr582entry:583 %m = icmp eq <4 x i32> %c, %d584 %v = select <4 x i1> %m, <4 x i32> %a, <4 x i32> %b585 ret <4 x i32> %v586 587 588 589}590 591define <4 x float> @test21(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {592; CHECK-LABEL: test21:593; CHECK: # %bb.0: # %entry594; CHECK-NEXT: xvcmpeqsp vs0, v4, v5595; CHECK-NEXT: xxsel v2, v3, v2, vs0596; CHECK-NEXT: blr597;598; CHECK-REG-LABEL: test21:599; CHECK-REG: # %bb.0: # %entry600; CHECK-REG-NEXT: xvcmpeqsp vs0, v4, v5601; CHECK-REG-NEXT: xxsel v2, v3, v2, vs0602; CHECK-REG-NEXT: blr603;604; CHECK-FISL-LABEL: test21:605; CHECK-FISL: # %bb.0: # %entry606; CHECK-FISL-NEXT: xvcmpeqsp vs0, v4, v5607; CHECK-FISL-NEXT: xxsel v2, v3, v2, vs0608; CHECK-FISL-NEXT: blr609;610; CHECK-LE-LABEL: test21:611; CHECK-LE: # %bb.0: # %entry612; CHECK-LE-NEXT: xvcmpeqsp vs0, v4, v5613; CHECK-LE-NEXT: xxsel v2, v3, v2, vs0614; CHECK-LE-NEXT: blr615entry:616 %m = fcmp oeq <4 x float> %c, %d617 %v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b618 ret <4 x float> %v619 620 621 622}623 624define <4 x float> @test22(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {625; CHECK-LABEL: test22:626; CHECK: # %bb.0: # %entry627; CHECK-NEXT: xvcmpgtsp vs0, v5, v4628; CHECK-NEXT: xvcmpgtsp vs1, v4, v5629; CHECK-NEXT: xxlor vs0, vs1, vs0630; CHECK-NEXT: xxsel v2, v2, v3, vs0631; CHECK-NEXT: blr632;633; CHECK-REG-LABEL: test22:634; CHECK-REG: # %bb.0: # %entry635; CHECK-REG-NEXT: xvcmpgtsp vs0, v5, v4636; CHECK-REG-NEXT: xvcmpgtsp vs1, v4, v5637; CHECK-REG-NEXT: xxlor vs0, vs1, vs0638; CHECK-REG-NEXT: xxsel v2, v2, v3, vs0639; CHECK-REG-NEXT: blr640;641; CHECK-FISL-LABEL: test22:642; CHECK-FISL: # %bb.0: # %entry643; CHECK-FISL-NEXT: xvcmpgtsp vs1, v5, v4644; CHECK-FISL-NEXT: xvcmpgtsp vs0, v4, v5645; CHECK-FISL-NEXT: xxlor vs0, vs0, vs1646; CHECK-FISL-NEXT: xxsel v2, v2, v3, vs0647; CHECK-FISL-NEXT: blr648;649; CHECK-LE-LABEL: test22:650; CHECK-LE: # %bb.0: # %entry651; CHECK-LE-NEXT: xvcmpgtsp vs0, v5, v4652; CHECK-LE-NEXT: xvcmpgtsp vs1, v4, v5653; CHECK-LE-NEXT: xxlor vs0, vs1, vs0654; CHECK-LE-NEXT: xxsel v2, v2, v3, vs0655; CHECK-LE-NEXT: blr656entry:657 %m = fcmp ueq <4 x float> %c, %d658 %v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b659 ret <4 x float> %v660 661 662 663}664 665define <8 x i16> @test23(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d) {666; CHECK-LABEL: test23:667; CHECK: # %bb.0: # %entry668; CHECK-NEXT: vcmpequh v4, v4, v5669; CHECK-NEXT: xxsel v2, v3, v2, v4670; CHECK-NEXT: blr671;672; CHECK-REG-LABEL: test23:673; CHECK-REG: # %bb.0: # %entry674; CHECK-REG-NEXT: vcmpequh v4, v4, v5675; CHECK-REG-NEXT: xxsel v2, v3, v2, v4676; CHECK-REG-NEXT: blr677;678; CHECK-FISL-LABEL: test23:679; CHECK-FISL: # %bb.0: # %entry680; CHECK-FISL-NEXT: vcmpequh v4, v4, v5681; CHECK-FISL-NEXT: xxlor vs0, v4, v4682; CHECK-FISL-NEXT: xxsel v2, v3, v2, vs0683; CHECK-FISL-NEXT: blr684;685; CHECK-LE-LABEL: test23:686; CHECK-LE: # %bb.0: # %entry687; CHECK-LE-NEXT: vcmpequh v4, v4, v5688; CHECK-LE-NEXT: xxsel v2, v3, v2, v4689; CHECK-LE-NEXT: blr690entry:691 %m = icmp eq <8 x i16> %c, %d692 %v = select <8 x i1> %m, <8 x i16> %a, <8 x i16> %b693 ret <8 x i16> %v694 695 696 697}698 699define <16 x i8> @test24(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) {700; CHECK-LABEL: test24:701; CHECK: # %bb.0: # %entry702; CHECK-NEXT: vcmpequb v4, v4, v5703; CHECK-NEXT: xxsel v2, v3, v2, v4704; CHECK-NEXT: blr705;706; CHECK-REG-LABEL: test24:707; CHECK-REG: # %bb.0: # %entry708; CHECK-REG-NEXT: vcmpequb v4, v4, v5709; CHECK-REG-NEXT: xxsel v2, v3, v2, v4710; CHECK-REG-NEXT: blr711;712; CHECK-FISL-LABEL: test24:713; CHECK-FISL: # %bb.0: # %entry714; CHECK-FISL-NEXT: vcmpequb v4, v4, v5715; CHECK-FISL-NEXT: xxlor vs0, v4, v4716; CHECK-FISL-NEXT: xxsel v2, v3, v2, vs0717; CHECK-FISL-NEXT: blr718;719; CHECK-LE-LABEL: test24:720; CHECK-LE: # %bb.0: # %entry721; CHECK-LE-NEXT: vcmpequb v4, v4, v5722; CHECK-LE-NEXT: xxsel v2, v3, v2, v4723; CHECK-LE-NEXT: blr724entry:725 %m = icmp eq <16 x i8> %c, %d726 %v = select <16 x i1> %m, <16 x i8> %a, <16 x i8> %b727 ret <16 x i8> %v728 729 730 731}732 733define <2 x double> @test25(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %d) {734; CHECK-LABEL: test25:735; CHECK: # %bb.0: # %entry736; CHECK-NEXT: xvcmpeqdp vs0, v4, v5737; CHECK-NEXT: xxsel v2, v3, v2, vs0738; CHECK-NEXT: blr739;740; CHECK-REG-LABEL: test25:741; CHECK-REG: # %bb.0: # %entry742; CHECK-REG-NEXT: xvcmpeqdp vs0, v4, v5743; CHECK-REG-NEXT: xxsel v2, v3, v2, vs0744; CHECK-REG-NEXT: blr745;746; CHECK-FISL-LABEL: test25:747; CHECK-FISL: # %bb.0: # %entry748; CHECK-FISL-NEXT: xvcmpeqdp vs0, v4, v5749; CHECK-FISL-NEXT: xxsel v2, v3, v2, vs0750; CHECK-FISL-NEXT: blr751;752; CHECK-LE-LABEL: test25:753; CHECK-LE: # %bb.0: # %entry754; CHECK-LE-NEXT: xvcmpeqdp v4, v4, v5755; CHECK-LE-NEXT: xxsel v2, v3, v2, v4756; CHECK-LE-NEXT: blr757entry:758 %m = fcmp oeq <2 x double> %c, %d759 %v = select <2 x i1> %m, <2 x double> %a, <2 x double> %b760 ret <2 x double> %v761 762 763}764 765define <2 x i64> @test26(<2 x i64> %a, <2 x i64> %b) {766; CHECK-LABEL: test26:767; CHECK: # %bb.0:768; CHECK-NEXT: addi r3, r1, -32769; CHECK-NEXT: stxvd2x v3, 0, r3770; CHECK-NEXT: addi r3, r1, -48771; CHECK-NEXT: stxvd2x v2, 0, r3772; CHECK-NEXT: ld r3, -24(r1)773; CHECK-NEXT: ld r4, -40(r1)774; CHECK-NEXT: add r3, r4, r3775; CHECK-NEXT: ld r4, -48(r1)776; CHECK-NEXT: std r3, -8(r1)777; CHECK-NEXT: ld r3, -32(r1)778; CHECK-NEXT: add r3, r4, r3779; CHECK-NEXT: std r3, -16(r1)780; CHECK-NEXT: addi r3, r1, -16781; CHECK-NEXT: lxvd2x v2, 0, r3782; CHECK-NEXT: blr783;784; CHECK-REG-LABEL: test26:785; CHECK-REG: # %bb.0:786; CHECK-REG-NEXT: addi r3, r1, -32787; CHECK-REG-NEXT: stxvd2x v3, 0, r3788; CHECK-REG-NEXT: addi r3, r1, -48789; CHECK-REG-NEXT: stxvd2x v2, 0, r3790; CHECK-REG-NEXT: ld r3, -24(r1)791; CHECK-REG-NEXT: ld r4, -40(r1)792; CHECK-REG-NEXT: add r3, r4, r3793; CHECK-REG-NEXT: ld r4, -48(r1)794; CHECK-REG-NEXT: std r3, -8(r1)795; CHECK-REG-NEXT: ld r3, -32(r1)796; CHECK-REG-NEXT: add r3, r4, r3797; CHECK-REG-NEXT: std r3, -16(r1)798; CHECK-REG-NEXT: addi r3, r1, -16799; CHECK-REG-NEXT: lxvd2x v2, 0, r3800; CHECK-REG-NEXT: blr801;802; CHECK-FISL-LABEL: test26:803; CHECK-FISL: # %bb.0:804; CHECK-FISL-NEXT: addi r3, r1, -32805; CHECK-FISL-NEXT: stxvd2x v3, 0, r3806; CHECK-FISL-NEXT: addi r3, r1, -48807; CHECK-FISL-NEXT: stxvd2x v2, 0, r3808; CHECK-FISL-NEXT: ld r4, -24(r1)809; CHECK-FISL-NEXT: ld r3, -40(r1)810; CHECK-FISL-NEXT: add r3, r3, r4811; CHECK-FISL-NEXT: std r3, -8(r1)812; CHECK-FISL-NEXT: ld r4, -32(r1)813; CHECK-FISL-NEXT: ld r3, -48(r1)814; CHECK-FISL-NEXT: add r3, r3, r4815; CHECK-FISL-NEXT: std r3, -16(r1)816; CHECK-FISL-NEXT: addi r3, r1, -16817; CHECK-FISL-NEXT: lxvd2x v2, 0, r3818; CHECK-FISL-NEXT: blr819;820; CHECK-LE-LABEL: test26:821; CHECK-LE: # %bb.0:822; CHECK-LE-NEXT: vaddudm v2, v2, v3823; CHECK-LE-NEXT: blr824 %v = add <2 x i64> %a, %b825 ret <2 x i64> %v826 827 828; Make sure we use only two stores (one for each operand).829 830; FIXME: The code quality here is not good; just make sure we do something for now.831 832}833 834define <2 x i64> @test27(<2 x i64> %a, <2 x i64> %b) {835; CHECK-LABEL: test27:836; CHECK: # %bb.0:837; CHECK-NEXT: xxland v2, v2, v3838; CHECK-NEXT: blr839;840; CHECK-REG-LABEL: test27:841; CHECK-REG: # %bb.0:842; CHECK-REG-NEXT: xxland v2, v2, v3843; CHECK-REG-NEXT: blr844;845; CHECK-FISL-LABEL: test27:846; CHECK-FISL: # %bb.0:847; CHECK-FISL-NEXT: xxland v2, v2, v3848; CHECK-FISL-NEXT: blr849;850; CHECK-LE-LABEL: test27:851; CHECK-LE: # %bb.0:852; CHECK-LE-NEXT: xxland v2, v2, v3853; CHECK-LE-NEXT: blr854 %v = and <2 x i64> %a, %b855 ret <2 x i64> %v856 857 858}859 860define <2 x double> @test28(ptr %a) {861; CHECK-LABEL: test28:862; CHECK: # %bb.0:863; CHECK-NEXT: lxvd2x v2, 0, r3864; CHECK-NEXT: blr865;866; CHECK-REG-LABEL: test28:867; CHECK-REG: # %bb.0:868; CHECK-REG-NEXT: lxvd2x v2, 0, r3869; CHECK-REG-NEXT: blr870;871; CHECK-FISL-LABEL: test28:872; CHECK-FISL: # %bb.0:873; CHECK-FISL-NEXT: lxvd2x v2, 0, r3874; CHECK-FISL-NEXT: blr875;876; CHECK-LE-LABEL: test28:877; CHECK-LE: # %bb.0:878; CHECK-LE-NEXT: lxvd2x vs0, 0, r3879; CHECK-LE-NEXT: xxswapd v2, vs0880; CHECK-LE-NEXT: blr881 %v = load <2 x double>, ptr %a, align 16882 ret <2 x double> %v883 884 885}886 887define void @test29(ptr %a, <2 x double> %b) {888; CHECK-LABEL: test29:889; CHECK: # %bb.0:890; CHECK-NEXT: stxvd2x v2, 0, r3891; CHECK-NEXT: blr892;893; CHECK-REG-LABEL: test29:894; CHECK-REG: # %bb.0:895; CHECK-REG-NEXT: stxvd2x v2, 0, r3896; CHECK-REG-NEXT: blr897;898; CHECK-FISL-LABEL: test29:899; CHECK-FISL: # %bb.0:900; CHECK-FISL-NEXT: stxvd2x v2, 0, r3901; CHECK-FISL-NEXT: blr902;903; CHECK-LE-LABEL: test29:904; CHECK-LE: # %bb.0:905; CHECK-LE-NEXT: xxswapd vs0, v2906; CHECK-LE-NEXT: stxvd2x vs0, 0, r3907; CHECK-LE-NEXT: blr908 store <2 x double> %b, ptr %a, align 16909 ret void910 911 912}913 914define <2 x double> @test28u(ptr %a) {915; CHECK-LABEL: test28u:916; CHECK: # %bb.0:917; CHECK-NEXT: lxvd2x v2, 0, r3918; CHECK-NEXT: blr919;920; CHECK-REG-LABEL: test28u:921; CHECK-REG: # %bb.0:922; CHECK-REG-NEXT: lxvd2x v2, 0, r3923; CHECK-REG-NEXT: blr924;925; CHECK-FISL-LABEL: test28u:926; CHECK-FISL: # %bb.0:927; CHECK-FISL-NEXT: lxvd2x v2, 0, r3928; CHECK-FISL-NEXT: blr929;930; CHECK-LE-LABEL: test28u:931; CHECK-LE: # %bb.0:932; CHECK-LE-NEXT: lxvd2x vs0, 0, r3933; CHECK-LE-NEXT: xxswapd v2, vs0934; CHECK-LE-NEXT: blr935 %v = load <2 x double>, ptr %a, align 8936 ret <2 x double> %v937 938 939}940 941define void @test29u(ptr %a, <2 x double> %b) {942; CHECK-LABEL: test29u:943; CHECK: # %bb.0:944; CHECK-NEXT: stxvd2x v2, 0, r3945; CHECK-NEXT: blr946;947; CHECK-REG-LABEL: test29u:948; CHECK-REG: # %bb.0:949; CHECK-REG-NEXT: stxvd2x v2, 0, r3950; CHECK-REG-NEXT: blr951;952; CHECK-FISL-LABEL: test29u:953; CHECK-FISL: # %bb.0:954; CHECK-FISL-NEXT: stxvd2x v2, 0, r3955; CHECK-FISL-NEXT: blr956;957; CHECK-LE-LABEL: test29u:958; CHECK-LE: # %bb.0:959; CHECK-LE-NEXT: xxswapd vs0, v2960; CHECK-LE-NEXT: stxvd2x vs0, 0, r3961; CHECK-LE-NEXT: blr962 store <2 x double> %b, ptr %a, align 8963 ret void964 965 966}967 968define <2 x i64> @test30(ptr %a) {969; CHECK-LABEL: test30:970; CHECK: # %bb.0:971; CHECK-NEXT: lxvd2x v2, 0, r3972; CHECK-NEXT: blr973;974; CHECK-REG-LABEL: test30:975; CHECK-REG: # %bb.0:976; CHECK-REG-NEXT: lxvd2x v2, 0, r3977; CHECK-REG-NEXT: blr978;979; CHECK-FISL-LABEL: test30:980; CHECK-FISL: # %bb.0:981; CHECK-FISL-NEXT: lxvd2x v2, 0, r3982; CHECK-FISL-NEXT: blr983;984; CHECK-LE-LABEL: test30:985; CHECK-LE: # %bb.0:986; CHECK-LE-NEXT: lxvd2x vs0, 0, r3987; CHECK-LE-NEXT: xxswapd v2, vs0988; CHECK-LE-NEXT: blr989 %v = load <2 x i64>, ptr %a, align 16990 ret <2 x i64> %v991 992 993 994}995 996define void @test31(ptr %a, <2 x i64> %b) {997; CHECK-LABEL: test31:998; CHECK: # %bb.0:999; CHECK-NEXT: stxvd2x v2, 0, r31000; CHECK-NEXT: blr1001;1002; CHECK-REG-LABEL: test31:1003; CHECK-REG: # %bb.0:1004; CHECK-REG-NEXT: stxvd2x v2, 0, r31005; CHECK-REG-NEXT: blr1006;1007; CHECK-FISL-LABEL: test31:1008; CHECK-FISL: # %bb.0:1009; CHECK-FISL-NEXT: stxvd2x v2, 0, r31010; CHECK-FISL-NEXT: blr1011;1012; CHECK-LE-LABEL: test31:1013; CHECK-LE: # %bb.0:1014; CHECK-LE-NEXT: xxswapd vs0, v21015; CHECK-LE-NEXT: stxvd2x vs0, 0, r31016; CHECK-LE-NEXT: blr1017 store <2 x i64> %b, ptr %a, align 161018 ret void1019 1020 1021}1022 1023define <4 x float> @test32(ptr %a) {1024; CHECK-LABEL: test32:1025; CHECK: # %bb.0:1026; CHECK-NEXT: lxvw4x v2, 0, r31027; CHECK-NEXT: blr1028;1029; CHECK-REG-LABEL: test32:1030; CHECK-REG: # %bb.0:1031; CHECK-REG-NEXT: lxvw4x v2, 0, r31032; CHECK-REG-NEXT: blr1033;1034; CHECK-FISL-LABEL: test32:1035; CHECK-FISL: # %bb.0:1036; CHECK-FISL-NEXT: lxvw4x v2, 0, r31037; CHECK-FISL-NEXT: blr1038;1039; CHECK-LE-LABEL: test32:1040; CHECK-LE: # %bb.0:1041; CHECK-LE-NEXT: lxvd2x vs0, 0, r31042; CHECK-LE-NEXT: xxswapd v2, vs01043; CHECK-LE-NEXT: blr1044 %v = load <4 x float>, ptr %a, align 161045 ret <4 x float> %v1046 1047 1048 1049}1050 1051define void @test33(ptr %a, <4 x float> %b) {1052; CHECK-LABEL: test33:1053; CHECK: # %bb.0:1054; CHECK-NEXT: stxvw4x v2, 0, r31055; CHECK-NEXT: blr1056;1057; CHECK-REG-LABEL: test33:1058; CHECK-REG: # %bb.0:1059; CHECK-REG-NEXT: stxvw4x v2, 0, r31060; CHECK-REG-NEXT: blr1061;1062; CHECK-FISL-LABEL: test33:1063; CHECK-FISL: # %bb.0:1064; CHECK-FISL-NEXT: stxvw4x v2, 0, r31065; CHECK-FISL-NEXT: blr1066;1067; CHECK-LE-LABEL: test33:1068; CHECK-LE: # %bb.0:1069; CHECK-LE-NEXT: xxswapd vs0, v21070; CHECK-LE-NEXT: stxvd2x vs0, 0, r31071; CHECK-LE-NEXT: blr1072 store <4 x float> %b, ptr %a, align 161073 ret void1074 1075 1076 1077}1078 1079define <4 x float> @test32u(ptr %a) {1080; CHECK-LABEL: test32u:1081; CHECK: # %bb.0:1082; CHECK-NEXT: li r4, 151083; CHECK-NEXT: lvsl v3, 0, r31084; CHECK-NEXT: lvx v2, r3, r41085; CHECK-NEXT: lvx v4, 0, r31086; CHECK-NEXT: vperm v2, v4, v2, v31087; CHECK-NEXT: blr1088;1089; CHECK-REG-LABEL: test32u:1090; CHECK-REG: # %bb.0:1091; CHECK-REG-NEXT: li r4, 151092; CHECK-REG-NEXT: lvsl v3, 0, r31093; CHECK-REG-NEXT: lvx v2, r3, r41094; CHECK-REG-NEXT: lvx v4, 0, r31095; CHECK-REG-NEXT: vperm v2, v4, v2, v31096; CHECK-REG-NEXT: blr1097;1098; CHECK-FISL-LABEL: test32u:1099; CHECK-FISL: # %bb.0:1100; CHECK-FISL-NEXT: li r4, 151101; CHECK-FISL-NEXT: lvx v3, r3, r41102; CHECK-FISL-NEXT: lvsl v4, 0, r31103; CHECK-FISL-NEXT: lvx v2, 0, r31104; CHECK-FISL-NEXT: vperm v2, v2, v3, v41105; CHECK-FISL-NEXT: blr1106;1107; CHECK-LE-LABEL: test32u:1108; CHECK-LE: # %bb.0:1109; CHECK-LE-NEXT: lxvd2x vs0, 0, r31110; CHECK-LE-NEXT: xxswapd v2, vs01111; CHECK-LE-NEXT: blr1112 %v = load <4 x float>, ptr %a, align 81113 ret <4 x float> %v1114 1115 1116}1117 1118define void @test33u(ptr %a, <4 x float> %b) {1119; CHECK-LABEL: test33u:1120; CHECK: # %bb.0:1121; CHECK-NEXT: stxvw4x v2, 0, r31122; CHECK-NEXT: blr1123;1124; CHECK-REG-LABEL: test33u:1125; CHECK-REG: # %bb.0:1126; CHECK-REG-NEXT: stxvw4x v2, 0, r31127; CHECK-REG-NEXT: blr1128;1129; CHECK-FISL-LABEL: test33u:1130; CHECK-FISL: # %bb.0:1131; CHECK-FISL-NEXT: stxvw4x v2, 0, r31132; CHECK-FISL-NEXT: blr1133;1134; CHECK-LE-LABEL: test33u:1135; CHECK-LE: # %bb.0:1136; CHECK-LE-NEXT: xxswapd vs0, v21137; CHECK-LE-NEXT: stxvd2x vs0, 0, r31138; CHECK-LE-NEXT: blr1139 store <4 x float> %b, ptr %a, align 81140 ret void1141 1142 1143 1144}1145 1146define <4 x i32> @test34(ptr %a) {1147; CHECK-LABEL: test34:1148; CHECK: # %bb.0:1149; CHECK-NEXT: lxvw4x v2, 0, r31150; CHECK-NEXT: blr1151;1152; CHECK-REG-LABEL: test34:1153; CHECK-REG: # %bb.0:1154; CHECK-REG-NEXT: lxvw4x v2, 0, r31155; CHECK-REG-NEXT: blr1156;1157; CHECK-FISL-LABEL: test34:1158; CHECK-FISL: # %bb.0:1159; CHECK-FISL-NEXT: lxvw4x v2, 0, r31160; CHECK-FISL-NEXT: blr1161;1162; CHECK-LE-LABEL: test34:1163; CHECK-LE: # %bb.0:1164; CHECK-LE-NEXT: lxvd2x vs0, 0, r31165; CHECK-LE-NEXT: xxswapd v2, vs01166; CHECK-LE-NEXT: blr1167 %v = load <4 x i32>, ptr %a, align 161168 ret <4 x i32> %v1169 1170 1171 1172}1173 1174define void @test35(ptr %a, <4 x i32> %b) {1175; CHECK-LABEL: test35:1176; CHECK: # %bb.0:1177; CHECK-NEXT: stxvw4x v2, 0, r31178; CHECK-NEXT: blr1179;1180; CHECK-REG-LABEL: test35:1181; CHECK-REG: # %bb.0:1182; CHECK-REG-NEXT: stxvw4x v2, 0, r31183; CHECK-REG-NEXT: blr1184;1185; CHECK-FISL-LABEL: test35:1186; CHECK-FISL: # %bb.0:1187; CHECK-FISL-NEXT: stxvw4x v2, 0, r31188; CHECK-FISL-NEXT: blr1189;1190; CHECK-LE-LABEL: test35:1191; CHECK-LE: # %bb.0:1192; CHECK-LE-NEXT: xxswapd vs0, v21193; CHECK-LE-NEXT: stxvd2x vs0, 0, r31194; CHECK-LE-NEXT: blr1195 store <4 x i32> %b, ptr %a, align 161196 ret void1197 1198 1199 1200}1201 1202define <2 x double> @test40(<2 x i64> %a) {1203; CHECK-LABEL: test40:1204; CHECK: # %bb.0:1205; CHECK-NEXT: xvcvuxddp v2, v21206; CHECK-NEXT: blr1207;1208; CHECK-REG-LABEL: test40:1209; CHECK-REG: # %bb.0:1210; CHECK-REG-NEXT: xvcvuxddp v2, v21211; CHECK-REG-NEXT: blr1212;1213; CHECK-FISL-LABEL: test40:1214; CHECK-FISL: # %bb.0:1215; CHECK-FISL-NEXT: xvcvuxddp v2, v21216; CHECK-FISL-NEXT: blr1217;1218; CHECK-LE-LABEL: test40:1219; CHECK-LE: # %bb.0:1220; CHECK-LE-NEXT: xvcvuxddp v2, v21221; CHECK-LE-NEXT: blr1222 %v = uitofp <2 x i64> %a to <2 x double>1223 ret <2 x double> %v1224 1225 1226}1227 1228define <2 x double> @test41(<2 x i64> %a) {1229; CHECK-LABEL: test41:1230; CHECK: # %bb.0:1231; CHECK-NEXT: xvcvsxddp v2, v21232; CHECK-NEXT: blr1233;1234; CHECK-REG-LABEL: test41:1235; CHECK-REG: # %bb.0:1236; CHECK-REG-NEXT: xvcvsxddp v2, v21237; CHECK-REG-NEXT: blr1238;1239; CHECK-FISL-LABEL: test41:1240; CHECK-FISL: # %bb.0:1241; CHECK-FISL-NEXT: xvcvsxddp v2, v21242; CHECK-FISL-NEXT: blr1243;1244; CHECK-LE-LABEL: test41:1245; CHECK-LE: # %bb.0:1246; CHECK-LE-NEXT: xvcvsxddp v2, v21247; CHECK-LE-NEXT: blr1248 %v = sitofp <2 x i64> %a to <2 x double>1249 ret <2 x double> %v1250 1251 1252}1253 1254define <2 x i64> @test42(<2 x double> %a) {1255; CHECK-LABEL: test42:1256; CHECK: # %bb.0:1257; CHECK-NEXT: xvcvdpuxds v2, v21258; CHECK-NEXT: blr1259;1260; CHECK-REG-LABEL: test42:1261; CHECK-REG: # %bb.0:1262; CHECK-REG-NEXT: xvcvdpuxds v2, v21263; CHECK-REG-NEXT: blr1264;1265; CHECK-FISL-LABEL: test42:1266; CHECK-FISL: # %bb.0:1267; CHECK-FISL-NEXT: xvcvdpuxds v2, v21268; CHECK-FISL-NEXT: blr1269;1270; CHECK-LE-LABEL: test42:1271; CHECK-LE: # %bb.0:1272; CHECK-LE-NEXT: xvcvdpuxds v2, v21273; CHECK-LE-NEXT: blr1274 %v = fptoui <2 x double> %a to <2 x i64>1275 ret <2 x i64> %v1276 1277 1278}1279 1280define <2 x i64> @test43(<2 x double> %a) {1281; CHECK-LABEL: test43:1282; CHECK: # %bb.0:1283; CHECK-NEXT: xvcvdpsxds v2, v21284; CHECK-NEXT: blr1285;1286; CHECK-REG-LABEL: test43:1287; CHECK-REG: # %bb.0:1288; CHECK-REG-NEXT: xvcvdpsxds v2, v21289; CHECK-REG-NEXT: blr1290;1291; CHECK-FISL-LABEL: test43:1292; CHECK-FISL: # %bb.0:1293; CHECK-FISL-NEXT: xvcvdpsxds v2, v21294; CHECK-FISL-NEXT: blr1295;1296; CHECK-LE-LABEL: test43:1297; CHECK-LE: # %bb.0:1298; CHECK-LE-NEXT: xvcvdpsxds v2, v21299; CHECK-LE-NEXT: blr1300 %v = fptosi <2 x double> %a to <2 x i64>1301 ret <2 x i64> %v1302 1303 1304}1305 1306define <2 x float> @test44(<2 x i64> %a) {1307; CHECK-LABEL: test44:1308; CHECK: # %bb.0:1309; CHECK-NEXT: addi r3, r1, -161310; CHECK-NEXT: stxvd2x v2, 0, r31311; CHECK-NEXT: ld r3, -8(r1)1312; CHECK-NEXT: std r3, -24(r1)1313; CHECK-NEXT: ld r3, -16(r1)1314; CHECK-NEXT: lfd f0, -24(r1)1315; CHECK-NEXT: std r3, -32(r1)1316; CHECK-NEXT: addi r3, r1, -481317; CHECK-NEXT: fcfidus f0, f01318; CHECK-NEXT: stfs f0, -48(r1)1319; CHECK-NEXT: lfd f0, -32(r1)1320; CHECK-NEXT: fcfidus f0, f01321; CHECK-NEXT: stfs f0, -64(r1)1322; CHECK-NEXT: lxvw4x vs0, 0, r31323; CHECK-NEXT: addi r3, r1, -641324; CHECK-NEXT: lxvw4x vs1, 0, r31325; CHECK-NEXT: xxmrghw v2, vs1, vs01326; CHECK-NEXT: blr1327;1328; CHECK-REG-LABEL: test44:1329; CHECK-REG: # %bb.0:1330; CHECK-REG-NEXT: addi r3, r1, -161331; CHECK-REG-NEXT: stxvd2x v2, 0, r31332; CHECK-REG-NEXT: ld r3, -8(r1)1333; CHECK-REG-NEXT: std r3, -24(r1)1334; CHECK-REG-NEXT: ld r3, -16(r1)1335; CHECK-REG-NEXT: lfd f0, -24(r1)1336; CHECK-REG-NEXT: std r3, -32(r1)1337; CHECK-REG-NEXT: addi r3, r1, -481338; CHECK-REG-NEXT: fcfidus f0, f01339; CHECK-REG-NEXT: stfs f0, -48(r1)1340; CHECK-REG-NEXT: lfd f0, -32(r1)1341; CHECK-REG-NEXT: fcfidus f0, f01342; CHECK-REG-NEXT: stfs f0, -64(r1)1343; CHECK-REG-NEXT: lxvw4x vs0, 0, r31344; CHECK-REG-NEXT: addi r3, r1, -641345; CHECK-REG-NEXT: lxvw4x vs1, 0, r31346; CHECK-REG-NEXT: xxmrghw v2, vs1, vs01347; CHECK-REG-NEXT: blr1348;1349; CHECK-FISL-LABEL: test44:1350; CHECK-FISL: # %bb.0:1351; CHECK-FISL-NEXT: addi r3, r1, -161352; CHECK-FISL-NEXT: stxvd2x v2, 0, r31353; CHECK-FISL-NEXT: ld r3, -8(r1)1354; CHECK-FISL-NEXT: std r3, -24(r1)1355; CHECK-FISL-NEXT: ld r3, -16(r1)1356; CHECK-FISL-NEXT: std r3, -32(r1)1357; CHECK-FISL-NEXT: lfd f0, -24(r1)1358; CHECK-FISL-NEXT: fcfidus f0, f01359; CHECK-FISL-NEXT: stfs f0, -48(r1)1360; CHECK-FISL-NEXT: lfd f0, -32(r1)1361; CHECK-FISL-NEXT: fcfidus f0, f01362; CHECK-FISL-NEXT: stfs f0, -64(r1)1363; CHECK-FISL-NEXT: addi r3, r1, -481364; CHECK-FISL-NEXT: lxvw4x vs1, 0, r31365; CHECK-FISL-NEXT: addi r3, r1, -641366; CHECK-FISL-NEXT: lxvw4x vs0, 0, r31367; CHECK-FISL-NEXT: xxmrghw v2, vs0, vs11368; CHECK-FISL-NEXT: blr1369;1370; CHECK-LE-LABEL: test44:1371; CHECK-LE: # %bb.0:1372; CHECK-LE-NEXT: xxswapd vs0, v21373; CHECK-LE-NEXT: xscvuxdsp f1, v21374; CHECK-LE-NEXT: xscvuxdsp f0, f01375; CHECK-LE-NEXT: xscvdpspn vs1, f11376; CHECK-LE-NEXT: xscvdpspn vs0, f01377; CHECK-LE-NEXT: xxmrghw v2, vs1, vs01378; CHECK-LE-NEXT: blr1379 %v = uitofp <2 x i64> %a to <2 x float>1380 ret <2 x float> %v1381 1382; FIXME: The code quality here looks pretty bad.1383}1384 1385define <2 x float> @test45(<2 x i64> %a) {1386; CHECK-LABEL: test45:1387; CHECK: # %bb.0:1388; CHECK-NEXT: addi r3, r1, -161389; CHECK-NEXT: stxvd2x v2, 0, r31390; CHECK-NEXT: ld r3, -8(r1)1391; CHECK-NEXT: std r3, -24(r1)1392; CHECK-NEXT: ld r3, -16(r1)1393; CHECK-NEXT: lfd f0, -24(r1)1394; CHECK-NEXT: std r3, -32(r1)1395; CHECK-NEXT: addi r3, r1, -481396; CHECK-NEXT: fcfids f0, f01397; CHECK-NEXT: stfs f0, -48(r1)1398; CHECK-NEXT: lfd f0, -32(r1)1399; CHECK-NEXT: fcfids f0, f01400; CHECK-NEXT: stfs f0, -64(r1)1401; CHECK-NEXT: lxvw4x vs0, 0, r31402; CHECK-NEXT: addi r3, r1, -641403; CHECK-NEXT: lxvw4x vs1, 0, r31404; CHECK-NEXT: xxmrghw v2, vs1, vs01405; CHECK-NEXT: blr1406;1407; CHECK-REG-LABEL: test45:1408; CHECK-REG: # %bb.0:1409; CHECK-REG-NEXT: addi r3, r1, -161410; CHECK-REG-NEXT: stxvd2x v2, 0, r31411; CHECK-REG-NEXT: ld r3, -8(r1)1412; CHECK-REG-NEXT: std r3, -24(r1)1413; CHECK-REG-NEXT: ld r3, -16(r1)1414; CHECK-REG-NEXT: lfd f0, -24(r1)1415; CHECK-REG-NEXT: std r3, -32(r1)1416; CHECK-REG-NEXT: addi r3, r1, -481417; CHECK-REG-NEXT: fcfids f0, f01418; CHECK-REG-NEXT: stfs f0, -48(r1)1419; CHECK-REG-NEXT: lfd f0, -32(r1)1420; CHECK-REG-NEXT: fcfids f0, f01421; CHECK-REG-NEXT: stfs f0, -64(r1)1422; CHECK-REG-NEXT: lxvw4x vs0, 0, r31423; CHECK-REG-NEXT: addi r3, r1, -641424; CHECK-REG-NEXT: lxvw4x vs1, 0, r31425; CHECK-REG-NEXT: xxmrghw v2, vs1, vs01426; CHECK-REG-NEXT: blr1427;1428; CHECK-FISL-LABEL: test45:1429; CHECK-FISL: # %bb.0:1430; CHECK-FISL-NEXT: addi r3, r1, -161431; CHECK-FISL-NEXT: stxvd2x v2, 0, r31432; CHECK-FISL-NEXT: ld r3, -8(r1)1433; CHECK-FISL-NEXT: std r3, -24(r1)1434; CHECK-FISL-NEXT: ld r3, -16(r1)1435; CHECK-FISL-NEXT: std r3, -32(r1)1436; CHECK-FISL-NEXT: lfd f0, -24(r1)1437; CHECK-FISL-NEXT: fcfids f0, f01438; CHECK-FISL-NEXT: stfs f0, -48(r1)1439; CHECK-FISL-NEXT: lfd f0, -32(r1)1440; CHECK-FISL-NEXT: fcfids f0, f01441; CHECK-FISL-NEXT: stfs f0, -64(r1)1442; CHECK-FISL-NEXT: addi r3, r1, -481443; CHECK-FISL-NEXT: lxvw4x vs1, 0, r31444; CHECK-FISL-NEXT: addi r3, r1, -641445; CHECK-FISL-NEXT: lxvw4x vs0, 0, r31446; CHECK-FISL-NEXT: xxmrghw v2, vs0, vs11447; CHECK-FISL-NEXT: blr1448;1449; CHECK-LE-LABEL: test45:1450; CHECK-LE: # %bb.0:1451; CHECK-LE-NEXT: xxswapd vs0, v21452; CHECK-LE-NEXT: xscvsxdsp f1, v21453; CHECK-LE-NEXT: xscvsxdsp f0, f01454; CHECK-LE-NEXT: xscvdpspn vs1, f11455; CHECK-LE-NEXT: xscvdpspn vs0, f01456; CHECK-LE-NEXT: xxmrghw v2, vs1, vs01457; CHECK-LE-NEXT: blr1458 %v = sitofp <2 x i64> %a to <2 x float>1459 ret <2 x float> %v1460 1461; FIXME: The code quality here looks pretty bad.1462}1463 1464define <2 x i64> @test46(<2 x float> %a) {1465; CHECK-LABEL: test46:1466; CHECK: # %bb.0:1467; CHECK-NEXT: addi r3, r1, -481468; CHECK-NEXT: stxvw4x v2, 0, r31469; CHECK-NEXT: lfs f0, -44(r1)1470; CHECK-NEXT: xscvdpuxds f0, f01471; CHECK-NEXT: stfd f0, -32(r1)1472; CHECK-NEXT: lfs f0, -48(r1)1473; CHECK-NEXT: ld r3, -32(r1)1474; CHECK-NEXT: xscvdpuxds f0, f01475; CHECK-NEXT: std r3, -8(r1)1476; CHECK-NEXT: stfd f0, -24(r1)1477; CHECK-NEXT: ld r3, -24(r1)1478; CHECK-NEXT: std r3, -16(r1)1479; CHECK-NEXT: addi r3, r1, -161480; CHECK-NEXT: lxvd2x v2, 0, r31481; CHECK-NEXT: blr1482;1483; CHECK-REG-LABEL: test46:1484; CHECK-REG: # %bb.0:1485; CHECK-REG-NEXT: addi r3, r1, -481486; CHECK-REG-NEXT: stxvw4x v2, 0, r31487; CHECK-REG-NEXT: lfs f0, -44(r1)1488; CHECK-REG-NEXT: xscvdpuxds f0, f01489; CHECK-REG-NEXT: stfd f0, -32(r1)1490; CHECK-REG-NEXT: lfs f0, -48(r1)1491; CHECK-REG-NEXT: ld r3, -32(r1)1492; CHECK-REG-NEXT: xscvdpuxds f0, f01493; CHECK-REG-NEXT: std r3, -8(r1)1494; CHECK-REG-NEXT: stfd f0, -24(r1)1495; CHECK-REG-NEXT: ld r3, -24(r1)1496; CHECK-REG-NEXT: std r3, -16(r1)1497; CHECK-REG-NEXT: addi r3, r1, -161498; CHECK-REG-NEXT: lxvd2x v2, 0, r31499; CHECK-REG-NEXT: blr1500;1501; CHECK-FISL-LABEL: test46:1502; CHECK-FISL: # %bb.0:1503; CHECK-FISL-NEXT: addi r3, r1, -481504; CHECK-FISL-NEXT: stxvw4x v2, 0, r31505; CHECK-FISL-NEXT: lfs f0, -44(r1)1506; CHECK-FISL-NEXT: xscvdpuxds f0, f01507; CHECK-FISL-NEXT: stfd f0, -32(r1)1508; CHECK-FISL-NEXT: lfs f0, -48(r1)1509; CHECK-FISL-NEXT: xscvdpuxds f0, f01510; CHECK-FISL-NEXT: stfd f0, -24(r1)1511; CHECK-FISL-NEXT: ld r3, -32(r1)1512; CHECK-FISL-NEXT: std r3, -8(r1)1513; CHECK-FISL-NEXT: ld r3, -24(r1)1514; CHECK-FISL-NEXT: std r3, -16(r1)1515; CHECK-FISL-NEXT: addi r3, r1, -161516; CHECK-FISL-NEXT: lxvd2x v2, 0, r31517; CHECK-FISL-NEXT: blr1518;1519; CHECK-LE-LABEL: test46:1520; CHECK-LE: # %bb.0:1521; CHECK-LE-NEXT: xxmrglw vs0, v2, v21522; CHECK-LE-NEXT: xvcvspdp vs0, vs01523; CHECK-LE-NEXT: xvcvdpuxds v2, vs01524; CHECK-LE-NEXT: blr1525 %v = fptoui <2 x float> %a to <2 x i64>1526 ret <2 x i64> %v1527 1528; FIXME: The code quality here looks pretty bad.1529}1530 1531define <2 x i64> @test47(<2 x float> %a) {1532; CHECK-LABEL: test47:1533; CHECK: # %bb.0:1534; CHECK-NEXT: addi r3, r1, -481535; CHECK-NEXT: stxvw4x v2, 0, r31536; CHECK-NEXT: lfs f0, -44(r1)1537; CHECK-NEXT: xscvdpsxds f0, f01538; CHECK-NEXT: stfd f0, -32(r1)1539; CHECK-NEXT: lfs f0, -48(r1)1540; CHECK-NEXT: ld r3, -32(r1)1541; CHECK-NEXT: xscvdpsxds f0, f01542; CHECK-NEXT: std r3, -8(r1)1543; CHECK-NEXT: stfd f0, -24(r1)1544; CHECK-NEXT: ld r3, -24(r1)1545; CHECK-NEXT: std r3, -16(r1)1546; CHECK-NEXT: addi r3, r1, -161547; CHECK-NEXT: lxvd2x v2, 0, r31548; CHECK-NEXT: blr1549;1550; CHECK-REG-LABEL: test47:1551; CHECK-REG: # %bb.0:1552; CHECK-REG-NEXT: addi r3, r1, -481553; CHECK-REG-NEXT: stxvw4x v2, 0, r31554; CHECK-REG-NEXT: lfs f0, -44(r1)1555; CHECK-REG-NEXT: xscvdpsxds f0, f01556; CHECK-REG-NEXT: stfd f0, -32(r1)1557; CHECK-REG-NEXT: lfs f0, -48(r1)1558; CHECK-REG-NEXT: ld r3, -32(r1)1559; CHECK-REG-NEXT: xscvdpsxds f0, f01560; CHECK-REG-NEXT: std r3, -8(r1)1561; CHECK-REG-NEXT: stfd f0, -24(r1)1562; CHECK-REG-NEXT: ld r3, -24(r1)1563; CHECK-REG-NEXT: std r3, -16(r1)1564; CHECK-REG-NEXT: addi r3, r1, -161565; CHECK-REG-NEXT: lxvd2x v2, 0, r31566; CHECK-REG-NEXT: blr1567;1568; CHECK-FISL-LABEL: test47:1569; CHECK-FISL: # %bb.0:1570; CHECK-FISL-NEXT: addi r3, r1, -481571; CHECK-FISL-NEXT: stxvw4x v2, 0, r31572; CHECK-FISL-NEXT: lfs f0, -44(r1)1573; CHECK-FISL-NEXT: xscvdpsxds f0, f01574; CHECK-FISL-NEXT: stfd f0, -32(r1)1575; CHECK-FISL-NEXT: lfs f0, -48(r1)1576; CHECK-FISL-NEXT: xscvdpsxds f0, f01577; CHECK-FISL-NEXT: stfd f0, -24(r1)1578; CHECK-FISL-NEXT: ld r3, -32(r1)1579; CHECK-FISL-NEXT: std r3, -8(r1)1580; CHECK-FISL-NEXT: ld r3, -24(r1)1581; CHECK-FISL-NEXT: std r3, -16(r1)1582; CHECK-FISL-NEXT: addi r3, r1, -161583; CHECK-FISL-NEXT: lxvd2x v2, 0, r31584; CHECK-FISL-NEXT: blr1585;1586; CHECK-LE-LABEL: test47:1587; CHECK-LE: # %bb.0:1588; CHECK-LE-NEXT: xxmrglw vs0, v2, v21589; CHECK-LE-NEXT: xvcvspdp vs0, vs01590; CHECK-LE-NEXT: xvcvdpsxds v2, vs01591; CHECK-LE-NEXT: blr1592 %v = fptosi <2 x float> %a to <2 x i64>1593 ret <2 x i64> %v1594 1595; FIXME: The code quality here looks pretty bad.1596}1597 1598define <2 x double> @test50(ptr %a) {1599; CHECK-LABEL: test50:1600; CHECK: # %bb.0:1601; CHECK-NEXT: lxvdsx v2, 0, r31602; CHECK-NEXT: blr1603;1604; CHECK-REG-LABEL: test50:1605; CHECK-REG: # %bb.0:1606; CHECK-REG-NEXT: lxvdsx v2, 0, r31607; CHECK-REG-NEXT: blr1608;1609; CHECK-FISL-LABEL: test50:1610; CHECK-FISL: # %bb.0:1611; CHECK-FISL-NEXT: lxvdsx v2, 0, r31612; CHECK-FISL-NEXT: blr1613;1614; CHECK-LE-LABEL: test50:1615; CHECK-LE: # %bb.0:1616; CHECK-LE-NEXT: lxvdsx v2, 0, r31617; CHECK-LE-NEXT: blr1618 %v = load double, ptr %a, align 81619 %w = insertelement <2 x double> undef, double %v, i32 01620 %x = insertelement <2 x double> %w, double %v, i32 11621 ret <2 x double> %x1622 1623 1624}1625 1626define <2 x double> @test51(<2 x double> %a, <2 x double> %b) {1627; CHECK-LABEL: test51:1628; CHECK: # %bb.0:1629; CHECK-NEXT: xxspltd v2, v2, 01630; CHECK-NEXT: blr1631;1632; CHECK-REG-LABEL: test51:1633; CHECK-REG: # %bb.0:1634; CHECK-REG-NEXT: xxspltd v2, v2, 01635; CHECK-REG-NEXT: blr1636;1637; CHECK-FISL-LABEL: test51:1638; CHECK-FISL: # %bb.0:1639; CHECK-FISL-NEXT: xxspltd v2, v2, 01640; CHECK-FISL-NEXT: blr1641;1642; CHECK-LE-LABEL: test51:1643; CHECK-LE: # %bb.0:1644; CHECK-LE-NEXT: xxspltd v2, v2, 11645; CHECK-LE-NEXT: blr1646 %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 0, i32 0>1647 ret <2 x double> %v1648 1649 1650}1651 1652define <2 x double> @test52(<2 x double> %a, <2 x double> %b) {1653; CHECK-LABEL: test52:1654; CHECK: # %bb.0:1655; CHECK-NEXT: xxmrghd v2, v2, v31656; CHECK-NEXT: blr1657;1658; CHECK-REG-LABEL: test52:1659; CHECK-REG: # %bb.0:1660; CHECK-REG-NEXT: xxmrghd v2, v2, v31661; CHECK-REG-NEXT: blr1662;1663; CHECK-FISL-LABEL: test52:1664; CHECK-FISL: # %bb.0:1665; CHECK-FISL-NEXT: xxmrghd v2, v2, v31666; CHECK-FISL-NEXT: blr1667;1668; CHECK-LE-LABEL: test52:1669; CHECK-LE: # %bb.0:1670; CHECK-LE-NEXT: xxmrgld v2, v3, v21671; CHECK-LE-NEXT: blr1672 %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 0, i32 2>1673 ret <2 x double> %v1674 1675 1676}1677 1678define <2 x double> @test53(<2 x double> %a, <2 x double> %b) {1679; CHECK-LABEL: test53:1680; CHECK: # %bb.0:1681; CHECK-NEXT: xxmrghd v2, v3, v21682; CHECK-NEXT: blr1683;1684; CHECK-REG-LABEL: test53:1685; CHECK-REG: # %bb.0:1686; CHECK-REG-NEXT: xxmrghd v2, v3, v21687; CHECK-REG-NEXT: blr1688;1689; CHECK-FISL-LABEL: test53:1690; CHECK-FISL: # %bb.0:1691; CHECK-FISL-NEXT: xxmrghd v2, v3, v21692; CHECK-FISL-NEXT: blr1693;1694; CHECK-LE-LABEL: test53:1695; CHECK-LE: # %bb.0:1696; CHECK-LE-NEXT: xxmrgld v2, v2, v31697; CHECK-LE-NEXT: blr1698 %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 2, i32 0>1699 ret <2 x double> %v1700 1701 1702}1703 1704define <2 x double> @test54(<2 x double> %a, <2 x double> %b) {1705; CHECK-LABEL: test54:1706; CHECK: # %bb.0:1707; CHECK-NEXT: xxpermdi v2, v2, v3, 21708; CHECK-NEXT: blr1709;1710; CHECK-REG-LABEL: test54:1711; CHECK-REG: # %bb.0:1712; CHECK-REG-NEXT: xxpermdi v2, v2, v3, 21713; CHECK-REG-NEXT: blr1714;1715; CHECK-FISL-LABEL: test54:1716; CHECK-FISL: # %bb.0:1717; CHECK-FISL-NEXT: xxpermdi v2, v2, v3, 21718; CHECK-FISL-NEXT: blr1719;1720; CHECK-LE-LABEL: test54:1721; CHECK-LE: # %bb.0:1722; CHECK-LE-NEXT: xxpermdi v2, v3, v2, 21723; CHECK-LE-NEXT: blr1724 %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 2>1725 ret <2 x double> %v1726 1727 1728}1729 1730define <2 x double> @test55(<2 x double> %a, <2 x double> %b) {1731; CHECK-LABEL: test55:1732; CHECK: # %bb.0:1733; CHECK-NEXT: xxmrgld v2, v2, v31734; CHECK-NEXT: blr1735;1736; CHECK-REG-LABEL: test55:1737; CHECK-REG: # %bb.0:1738; CHECK-REG-NEXT: xxmrgld v2, v2, v31739; CHECK-REG-NEXT: blr1740;1741; CHECK-FISL-LABEL: test55:1742; CHECK-FISL: # %bb.0:1743; CHECK-FISL-NEXT: xxmrgld v2, v2, v31744; CHECK-FISL-NEXT: blr1745;1746; CHECK-LE-LABEL: test55:1747; CHECK-LE: # %bb.0:1748; CHECK-LE-NEXT: xxmrghd v2, v3, v21749; CHECK-LE-NEXT: blr1750 %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 3>1751 ret <2 x double> %v1752 1753 1754}1755 1756define <2 x i64> @test56(<2 x i64> %a, <2 x i64> %b) {1757; CHECK-LABEL: test56:1758; CHECK: # %bb.0:1759; CHECK-NEXT: xxmrgld v2, v2, v31760; CHECK-NEXT: blr1761;1762; CHECK-REG-LABEL: test56:1763; CHECK-REG: # %bb.0:1764; CHECK-REG-NEXT: xxmrgld v2, v2, v31765; CHECK-REG-NEXT: blr1766;1767; CHECK-FISL-LABEL: test56:1768; CHECK-FISL: # %bb.0:1769; CHECK-FISL-NEXT: xxmrgld v2, v2, v31770; CHECK-FISL-NEXT: blr1771;1772; CHECK-LE-LABEL: test56:1773; CHECK-LE: # %bb.0:1774; CHECK-LE-NEXT: xxmrghd v2, v3, v21775; CHECK-LE-NEXT: blr1776 %v = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 3>1777 ret <2 x i64> %v1778 1779 1780}1781 1782define <2 x i64> @test60(<2 x i64> %a, <2 x i64> %b) {1783; CHECK-LABEL: test60:1784; CHECK: # %bb.0:1785; CHECK-NEXT: addi r3, r1, -321786; CHECK-NEXT: stxvd2x v3, 0, r31787; CHECK-NEXT: addi r3, r1, -481788; CHECK-NEXT: stxvd2x v2, 0, r31789; CHECK-NEXT: lwz r3, -20(r1)1790; CHECK-NEXT: ld r4, -40(r1)1791; CHECK-NEXT: sld r3, r4, r31792; CHECK-NEXT: ld r4, -48(r1)1793; CHECK-NEXT: std r3, -8(r1)1794; CHECK-NEXT: lwz r3, -28(r1)1795; CHECK-NEXT: sld r3, r4, r31796; CHECK-NEXT: std r3, -16(r1)1797; CHECK-NEXT: addi r3, r1, -161798; CHECK-NEXT: lxvd2x v2, 0, r31799; CHECK-NEXT: blr1800;1801; CHECK-REG-LABEL: test60:1802; CHECK-REG: # %bb.0:1803; CHECK-REG-NEXT: addi r3, r1, -321804; CHECK-REG-NEXT: stxvd2x v3, 0, r31805; CHECK-REG-NEXT: addi r3, r1, -481806; CHECK-REG-NEXT: stxvd2x v2, 0, r31807; CHECK-REG-NEXT: lwz r3, -20(r1)1808; CHECK-REG-NEXT: ld r4, -40(r1)1809; CHECK-REG-NEXT: sld r3, r4, r31810; CHECK-REG-NEXT: ld r4, -48(r1)1811; CHECK-REG-NEXT: std r3, -8(r1)1812; CHECK-REG-NEXT: lwz r3, -28(r1)1813; CHECK-REG-NEXT: sld r3, r4, r31814; CHECK-REG-NEXT: std r3, -16(r1)1815; CHECK-REG-NEXT: addi r3, r1, -161816; CHECK-REG-NEXT: lxvd2x v2, 0, r31817; CHECK-REG-NEXT: blr1818;1819; CHECK-FISL-LABEL: test60:1820; CHECK-FISL: # %bb.0:1821; CHECK-FISL-NEXT: addi r3, r1, -321822; CHECK-FISL-NEXT: stxvd2x v3, 0, r31823; CHECK-FISL-NEXT: addi r3, r1, -481824; CHECK-FISL-NEXT: stxvd2x v2, 0, r31825; CHECK-FISL-NEXT: lwz r4, -20(r1)1826; CHECK-FISL-NEXT: ld r3, -40(r1)1827; CHECK-FISL-NEXT: sld r3, r3, r41828; CHECK-FISL-NEXT: std r3, -8(r1)1829; CHECK-FISL-NEXT: lwz r4, -28(r1)1830; CHECK-FISL-NEXT: ld r3, -48(r1)1831; CHECK-FISL-NEXT: sld r3, r3, r41832; CHECK-FISL-NEXT: std r3, -16(r1)1833; CHECK-FISL-NEXT: addi r3, r1, -161834; CHECK-FISL-NEXT: lxvd2x v2, 0, r31835; CHECK-FISL-NEXT: blr1836;1837; CHECK-LE-LABEL: test60:1838; CHECK-LE: # %bb.0:1839; CHECK-LE-NEXT: vsld v2, v2, v31840; CHECK-LE-NEXT: blr1841 %v = shl <2 x i64> %a, %b1842 ret <2 x i64> %v1843 1844; This should scalarize, and the current code quality is not good.1845}1846 1847define <2 x i64> @test61(<2 x i64> %a, <2 x i64> %b) {1848; CHECK-LABEL: test61:1849; CHECK: # %bb.0:1850; CHECK-NEXT: addi r3, r1, -321851; CHECK-NEXT: stxvd2x v3, 0, r31852; CHECK-NEXT: addi r3, r1, -481853; CHECK-NEXT: stxvd2x v2, 0, r31854; CHECK-NEXT: lwz r3, -20(r1)1855; CHECK-NEXT: ld r4, -40(r1)1856; CHECK-NEXT: srd r3, r4, r31857; CHECK-NEXT: ld r4, -48(r1)1858; CHECK-NEXT: std r3, -8(r1)1859; CHECK-NEXT: lwz r3, -28(r1)1860; CHECK-NEXT: srd r3, r4, r31861; CHECK-NEXT: std r3, -16(r1)1862; CHECK-NEXT: addi r3, r1, -161863; CHECK-NEXT: lxvd2x v2, 0, r31864; CHECK-NEXT: blr1865;1866; CHECK-REG-LABEL: test61:1867; CHECK-REG: # %bb.0:1868; CHECK-REG-NEXT: addi r3, r1, -321869; CHECK-REG-NEXT: stxvd2x v3, 0, r31870; CHECK-REG-NEXT: addi r3, r1, -481871; CHECK-REG-NEXT: stxvd2x v2, 0, r31872; CHECK-REG-NEXT: lwz r3, -20(r1)1873; CHECK-REG-NEXT: ld r4, -40(r1)1874; CHECK-REG-NEXT: srd r3, r4, r31875; CHECK-REG-NEXT: ld r4, -48(r1)1876; CHECK-REG-NEXT: std r3, -8(r1)1877; CHECK-REG-NEXT: lwz r3, -28(r1)1878; CHECK-REG-NEXT: srd r3, r4, r31879; CHECK-REG-NEXT: std r3, -16(r1)1880; CHECK-REG-NEXT: addi r3, r1, -161881; CHECK-REG-NEXT: lxvd2x v2, 0, r31882; CHECK-REG-NEXT: blr1883;1884; CHECK-FISL-LABEL: test61:1885; CHECK-FISL: # %bb.0:1886; CHECK-FISL-NEXT: addi r3, r1, -321887; CHECK-FISL-NEXT: stxvd2x v3, 0, r31888; CHECK-FISL-NEXT: addi r3, r1, -481889; CHECK-FISL-NEXT: stxvd2x v2, 0, r31890; CHECK-FISL-NEXT: lwz r4, -20(r1)1891; CHECK-FISL-NEXT: ld r3, -40(r1)1892; CHECK-FISL-NEXT: srd r3, r3, r41893; CHECK-FISL-NEXT: std r3, -8(r1)1894; CHECK-FISL-NEXT: lwz r4, -28(r1)1895; CHECK-FISL-NEXT: ld r3, -48(r1)1896; CHECK-FISL-NEXT: srd r3, r3, r41897; CHECK-FISL-NEXT: std r3, -16(r1)1898; CHECK-FISL-NEXT: addi r3, r1, -161899; CHECK-FISL-NEXT: lxvd2x v2, 0, r31900; CHECK-FISL-NEXT: blr1901;1902; CHECK-LE-LABEL: test61:1903; CHECK-LE: # %bb.0:1904; CHECK-LE-NEXT: vsrd v2, v2, v31905; CHECK-LE-NEXT: blr1906 %v = lshr <2 x i64> %a, %b1907 ret <2 x i64> %v1908 1909; This should scalarize, and the current code quality is not good.1910}1911 1912define <2 x i64> @test62(<2 x i64> %a, <2 x i64> %b) {1913; CHECK-LABEL: test62:1914; CHECK: # %bb.0:1915; CHECK-NEXT: addi r3, r1, -321916; CHECK-NEXT: stxvd2x v3, 0, r31917; CHECK-NEXT: addi r3, r1, -481918; CHECK-NEXT: stxvd2x v2, 0, r31919; CHECK-NEXT: lwz r3, -20(r1)1920; CHECK-NEXT: ld r4, -40(r1)1921; CHECK-NEXT: srad r3, r4, r31922; CHECK-NEXT: ld r4, -48(r1)1923; CHECK-NEXT: std r3, -8(r1)1924; CHECK-NEXT: lwz r3, -28(r1)1925; CHECK-NEXT: srad r3, r4, r31926; CHECK-NEXT: std r3, -16(r1)1927; CHECK-NEXT: addi r3, r1, -161928; CHECK-NEXT: lxvd2x v2, 0, r31929; CHECK-NEXT: blr1930;1931; CHECK-REG-LABEL: test62:1932; CHECK-REG: # %bb.0:1933; CHECK-REG-NEXT: addi r3, r1, -321934; CHECK-REG-NEXT: stxvd2x v3, 0, r31935; CHECK-REG-NEXT: addi r3, r1, -481936; CHECK-REG-NEXT: stxvd2x v2, 0, r31937; CHECK-REG-NEXT: lwz r3, -20(r1)1938; CHECK-REG-NEXT: ld r4, -40(r1)1939; CHECK-REG-NEXT: srad r3, r4, r31940; CHECK-REG-NEXT: ld r4, -48(r1)1941; CHECK-REG-NEXT: std r3, -8(r1)1942; CHECK-REG-NEXT: lwz r3, -28(r1)1943; CHECK-REG-NEXT: srad r3, r4, r31944; CHECK-REG-NEXT: std r3, -16(r1)1945; CHECK-REG-NEXT: addi r3, r1, -161946; CHECK-REG-NEXT: lxvd2x v2, 0, r31947; CHECK-REG-NEXT: blr1948;1949; CHECK-FISL-LABEL: test62:1950; CHECK-FISL: # %bb.0:1951; CHECK-FISL-NEXT: addi r3, r1, -321952; CHECK-FISL-NEXT: stxvd2x v3, 0, r31953; CHECK-FISL-NEXT: addi r3, r1, -481954; CHECK-FISL-NEXT: stxvd2x v2, 0, r31955; CHECK-FISL-NEXT: lwz r4, -20(r1)1956; CHECK-FISL-NEXT: ld r3, -40(r1)1957; CHECK-FISL-NEXT: srad r3, r3, r41958; CHECK-FISL-NEXT: std r3, -8(r1)1959; CHECK-FISL-NEXT: lwz r4, -28(r1)1960; CHECK-FISL-NEXT: ld r3, -48(r1)1961; CHECK-FISL-NEXT: srad r3, r3, r41962; CHECK-FISL-NEXT: std r3, -16(r1)1963; CHECK-FISL-NEXT: addi r3, r1, -161964; CHECK-FISL-NEXT: lxvd2x v2, 0, r31965; CHECK-FISL-NEXT: blr1966;1967; CHECK-LE-LABEL: test62:1968; CHECK-LE: # %bb.0:1969; CHECK-LE-NEXT: vsrad v2, v2, v31970; CHECK-LE-NEXT: blr1971 %v = ashr <2 x i64> %a, %b1972 ret <2 x i64> %v1973 1974; This should scalarize, and the current code quality is not good.1975}1976 1977define double @test63(<2 x double> %a) {1978; CHECK-LABEL: test63:1979; CHECK: # %bb.0:1980; CHECK-NEXT: xxlor f1, v2, v21981; CHECK-NEXT: blr1982;1983; CHECK-REG-LABEL: test63:1984; CHECK-REG: # %bb.0:1985; CHECK-REG-NEXT: xxlor f1, v2, v21986; CHECK-REG-NEXT: blr1987;1988; CHECK-FISL-LABEL: test63:1989; CHECK-FISL: # %bb.0:1990; CHECK-FISL-NEXT: xxlor f1, v2, v21991; CHECK-FISL-NEXT: blr1992;1993; CHECK-LE-LABEL: test63:1994; CHECK-LE: # %bb.0:1995; CHECK-LE-NEXT: xxswapd vs1, v21996; CHECK-LE-NEXT: blr1997 %v = extractelement <2 x double> %a, i32 01998 ret double %v1999 2000 2001 2002}2003 2004define double @test64(<2 x double> %a) {2005; CHECK-LABEL: test64:2006; CHECK: # %bb.0:2007; CHECK-NEXT: xxswapd vs1, v22008; CHECK-NEXT: blr2009;2010; CHECK-REG-LABEL: test64:2011; CHECK-REG: # %bb.0:2012; CHECK-REG-NEXT: xxswapd vs1, v22013; CHECK-REG-NEXT: blr2014;2015; CHECK-FISL-LABEL: test64:2016; CHECK-FISL: # %bb.0:2017; CHECK-FISL-NEXT: xxswapd vs0, v22018; CHECK-FISL-NEXT: fmr f1, f02019; CHECK-FISL-NEXT: blr2020;2021; CHECK-LE-LABEL: test64:2022; CHECK-LE: # %bb.0:2023; CHECK-LE-NEXT: xxlor f1, v2, v22024; CHECK-LE-NEXT: blr2025 %v = extractelement <2 x double> %a, i32 12026 ret double %v2027 2028 2029 2030}2031 2032define <2 x i1> @test65(<2 x i64> %a, <2 x i64> %b) {2033; CHECK-LABEL: test65:2034; CHECK: # %bb.0:2035; CHECK-NEXT: addis r3, r2, .LCPI59_0@toc@ha2036; CHECK-NEXT: vcmpequw v2, v2, v32037; CHECK-NEXT: addi r3, r3, .LCPI59_0@toc@l2038; CHECK-NEXT: lxvw4x v3, 0, r32039; CHECK-NEXT: vperm v3, v2, v2, v32040; CHECK-NEXT: xxland v2, v3, v22041; CHECK-NEXT: blr2042;2043; CHECK-REG-LABEL: test65:2044; CHECK-REG: # %bb.0:2045; CHECK-REG-NEXT: addis r3, r2, .LCPI59_0@toc@ha2046; CHECK-REG-NEXT: vcmpequw v2, v2, v32047; CHECK-REG-NEXT: addi r3, r3, .LCPI59_0@toc@l2048; CHECK-REG-NEXT: lxvw4x v3, 0, r32049; CHECK-REG-NEXT: vperm v3, v2, v2, v32050; CHECK-REG-NEXT: xxland v2, v3, v22051; CHECK-REG-NEXT: blr2052;2053; CHECK-FISL-LABEL: test65:2054; CHECK-FISL: # %bb.0:2055; CHECK-FISL-NEXT: vcmpequw v3, v2, v32056; CHECK-FISL-NEXT: addis r3, r2, .LCPI59_0@toc@ha2057; CHECK-FISL-NEXT: addi r3, r3, .LCPI59_0@toc@l2058; CHECK-FISL-NEXT: lxvw4x v2, 0, r32059; CHECK-FISL-NEXT: vperm v2, v3, v3, v22060; CHECK-FISL-NEXT: xxland v2, v2, v32061; CHECK-FISL-NEXT: blr2062;2063; CHECK-LE-LABEL: test65:2064; CHECK-LE: # %bb.0:2065; CHECK-LE-NEXT: vcmpequd v2, v2, v32066; CHECK-LE-NEXT: blr2067 %w = icmp eq <2 x i64> %a, %b2068 ret <2 x i1> %w2069 2070 2071 2072}2073 2074define <2 x i1> @test66(<2 x i64> %a, <2 x i64> %b) {2075; CHECK-LABEL: test66:2076; CHECK: # %bb.0:2077; CHECK-NEXT: addis r3, r2, .LCPI60_0@toc@ha2078; CHECK-NEXT: vcmpequw v2, v2, v32079; CHECK-NEXT: addi r3, r3, .LCPI60_0@toc@l2080; CHECK-NEXT: lxvw4x v3, 0, r32081; CHECK-NEXT: xxlnor v2, v2, v22082; CHECK-NEXT: vperm v3, v2, v2, v32083; CHECK-NEXT: xxlor v2, v3, v22084; CHECK-NEXT: blr2085;2086; CHECK-REG-LABEL: test66:2087; CHECK-REG: # %bb.0:2088; CHECK-REG-NEXT: addis r3, r2, .LCPI60_0@toc@ha2089; CHECK-REG-NEXT: vcmpequw v2, v2, v32090; CHECK-REG-NEXT: addi r3, r3, .LCPI60_0@toc@l2091; CHECK-REG-NEXT: lxvw4x v3, 0, r32092; CHECK-REG-NEXT: xxlnor v2, v2, v22093; CHECK-REG-NEXT: vperm v3, v2, v2, v32094; CHECK-REG-NEXT: xxlor v2, v3, v22095; CHECK-REG-NEXT: blr2096;2097; CHECK-FISL-LABEL: test66:2098; CHECK-FISL: # %bb.0:2099; CHECK-FISL-NEXT: vcmpequw v2, v2, v32100; CHECK-FISL-NEXT: xxlnor v3, v2, v22101; CHECK-FISL-NEXT: addis r3, r2, .LCPI60_0@toc@ha2102; CHECK-FISL-NEXT: addi r3, r3, .LCPI60_0@toc@l2103; CHECK-FISL-NEXT: lxvw4x v2, 0, r32104; CHECK-FISL-NEXT: vperm v2, v3, v3, v22105; CHECK-FISL-NEXT: xxlor v2, v2, v32106; CHECK-FISL-NEXT: blr2107;2108; CHECK-LE-LABEL: test66:2109; CHECK-LE: # %bb.0:2110; CHECK-LE-NEXT: vcmpequd v2, v2, v32111; CHECK-LE-NEXT: xxlnor v2, v2, v22112; CHECK-LE-NEXT: blr2113 %w = icmp ne <2 x i64> %a, %b2114 ret <2 x i1> %w2115 2116 2117 2118}2119 2120define <2 x i1> @test67(<2 x i64> %a, <2 x i64> %b) {2121; CHECK-LABEL: test67:2122; CHECK: # %bb.0:2123; CHECK-NEXT: addi r3, r1, -322124; CHECK-NEXT: stxvd2x v3, 0, r32125; CHECK-NEXT: addi r3, r1, -482126; CHECK-NEXT: stxvd2x v2, 0, r32127; CHECK-NEXT: ld r3, -24(r1)2128; CHECK-NEXT: ld r4, -40(r1)2129; CHECK-NEXT: ld r6, -48(r1)2130; CHECK-NEXT: cmpld r4, r32131; CHECK-NEXT: li r3, 02132; CHECK-NEXT: li r4, -12133; CHECK-NEXT: isellt r5, r4, r32134; CHECK-NEXT: std r5, -8(r1)2135; CHECK-NEXT: ld r5, -32(r1)2136; CHECK-NEXT: cmpld r6, r52137; CHECK-NEXT: isellt r3, r4, r32138; CHECK-NEXT: std r3, -16(r1)2139; CHECK-NEXT: addi r3, r1, -162140; CHECK-NEXT: lxvd2x v2, 0, r32141; CHECK-NEXT: blr2142;2143; CHECK-REG-LABEL: test67:2144; CHECK-REG: # %bb.0:2145; CHECK-REG-NEXT: addi r3, r1, -322146; CHECK-REG-NEXT: stxvd2x v3, 0, r32147; CHECK-REG-NEXT: addi r3, r1, -482148; CHECK-REG-NEXT: stxvd2x v2, 0, r32149; CHECK-REG-NEXT: ld r3, -24(r1)2150; CHECK-REG-NEXT: ld r4, -40(r1)2151; CHECK-REG-NEXT: ld r6, -48(r1)2152; CHECK-REG-NEXT: cmpld r4, r32153; CHECK-REG-NEXT: li r3, 02154; CHECK-REG-NEXT: li r4, -12155; CHECK-REG-NEXT: isellt r5, r4, r32156; CHECK-REG-NEXT: std r5, -8(r1)2157; CHECK-REG-NEXT: ld r5, -32(r1)2158; CHECK-REG-NEXT: cmpld r6, r52159; CHECK-REG-NEXT: isellt r3, r4, r32160; CHECK-REG-NEXT: std r3, -16(r1)2161; CHECK-REG-NEXT: addi r3, r1, -162162; CHECK-REG-NEXT: lxvd2x v2, 0, r32163; CHECK-REG-NEXT: blr2164;2165; CHECK-FISL-LABEL: test67:2166; CHECK-FISL: # %bb.0:2167; CHECK-FISL-NEXT: addi r3, r1, -322168; CHECK-FISL-NEXT: stxvd2x v3, 0, r32169; CHECK-FISL-NEXT: addi r3, r1, -482170; CHECK-FISL-NEXT: stxvd2x v2, 0, r32171; CHECK-FISL-NEXT: ld r4, -24(r1)2172; CHECK-FISL-NEXT: ld r3, -40(r1)2173; CHECK-FISL-NEXT: cmpld r3, r42174; CHECK-FISL-NEXT: li r4, 02175; CHECK-FISL-NEXT: li r3, -12176; CHECK-FISL-NEXT: isellt r5, r3, r42177; CHECK-FISL-NEXT: std r5, -8(r1)2178; CHECK-FISL-NEXT: ld r6, -32(r1)2179; CHECK-FISL-NEXT: ld r5, -48(r1)2180; CHECK-FISL-NEXT: cmpld r5, r62181; CHECK-FISL-NEXT: isellt r3, r3, r42182; CHECK-FISL-NEXT: std r3, -16(r1)2183; CHECK-FISL-NEXT: addi r3, r1, -162184; CHECK-FISL-NEXT: lxvd2x v2, 0, r32185; CHECK-FISL-NEXT: blr2186;2187; CHECK-LE-LABEL: test67:2188; CHECK-LE: # %bb.0:2189; CHECK-LE-NEXT: vcmpgtud v2, v3, v22190; CHECK-LE-NEXT: blr2191 %w = icmp ult <2 x i64> %a, %b2192 ret <2 x i1> %w2193 2194; This should scalarize, and the current code quality is not good.2195 2196}2197 2198define <2 x double> @test68(<2 x i32> %a) {2199; CHECK-LABEL: test68:2200; CHECK: # %bb.0:2201; CHECK-NEXT: xxmrghw vs0, v2, v22202; CHECK-NEXT: xvcvsxwdp v2, vs02203; CHECK-NEXT: blr2204;2205; CHECK-REG-LABEL: test68:2206; CHECK-REG: # %bb.0:2207; CHECK-REG-NEXT: xxmrghw vs0, v2, v22208; CHECK-REG-NEXT: xvcvsxwdp v2, vs02209; CHECK-REG-NEXT: blr2210;2211; CHECK-FISL-LABEL: test68:2212; CHECK-FISL: # %bb.0:2213; CHECK-FISL-NEXT: xxmrghw vs0, v2, v22214; CHECK-FISL-NEXT: xvcvsxwdp v2, vs02215; CHECK-FISL-NEXT: blr2216;2217; CHECK-LE-LABEL: test68:2218; CHECK-LE: # %bb.0:2219; CHECK-LE-NEXT: xxmrglw v2, v2, v22220; CHECK-LE-NEXT: xvcvsxwdp v2, v22221; CHECK-LE-NEXT: blr2222 %w = sitofp <2 x i32> %a to <2 x double>2223 ret <2 x double> %w2224 2225 2226}2227 2228; This gets scalarized so the code isn't great2229define <2 x double> @test69(<2 x i16> %a) {2230; CHECK-LABEL: test69:2231; CHECK: # %bb.0:2232; CHECK-NEXT: addis r3, r2, .LCPI63_0@toc@ha2233; CHECK-NEXT: addi r3, r3, .LCPI63_0@toc@l2234; CHECK-NEXT: lxvw4x v3, 0, r32235; CHECK-NEXT: addi r3, r1, -322236; CHECK-NEXT: vperm v2, v2, v2, v32237; CHECK-NEXT: stxvd2x v2, 0, r32238; CHECK-NEXT: lha r3, -18(r1)2239; CHECK-NEXT: std r3, -8(r1)2240; CHECK-NEXT: lha r3, -26(r1)2241; CHECK-NEXT: std r3, -16(r1)2242; CHECK-NEXT: addi r3, r1, -162243; CHECK-NEXT: lxvd2x v2, 0, r32244; CHECK-NEXT: xvcvsxddp v2, v22245; CHECK-NEXT: blr2246;2247; CHECK-REG-LABEL: test69:2248; CHECK-REG: # %bb.0:2249; CHECK-REG-NEXT: addis r3, r2, .LCPI63_0@toc@ha2250; CHECK-REG-NEXT: addi r3, r3, .LCPI63_0@toc@l2251; CHECK-REG-NEXT: lxvw4x v3, 0, r32252; CHECK-REG-NEXT: addi r3, r1, -322253; CHECK-REG-NEXT: vperm v2, v2, v2, v32254; CHECK-REG-NEXT: stxvd2x v2, 0, r32255; CHECK-REG-NEXT: lha r3, -18(r1)2256; CHECK-REG-NEXT: std r3, -8(r1)2257; CHECK-REG-NEXT: lha r3, -26(r1)2258; CHECK-REG-NEXT: std r3, -16(r1)2259; CHECK-REG-NEXT: addi r3, r1, -162260; CHECK-REG-NEXT: lxvd2x v2, 0, r32261; CHECK-REG-NEXT: xvcvsxddp v2, v22262; CHECK-REG-NEXT: blr2263;2264; CHECK-FISL-LABEL: test69:2265; CHECK-FISL: # %bb.0:2266; CHECK-FISL-NEXT: addis r3, r2, .LCPI63_0@toc@ha2267; CHECK-FISL-NEXT: addi r3, r3, .LCPI63_0@toc@l2268; CHECK-FISL-NEXT: lxvw4x v3, 0, r32269; CHECK-FISL-NEXT: vperm v2, v2, v2, v32270; CHECK-FISL-NEXT: xxlor vs0, v2, v22271; CHECK-FISL-NEXT: addi r3, r1, -322272; CHECK-FISL-NEXT: stxvd2x vs0, 0, r32273; CHECK-FISL-NEXT: lha r3, -18(r1)2274; CHECK-FISL-NEXT: std r3, -8(r1)2275; CHECK-FISL-NEXT: lha r3, -26(r1)2276; CHECK-FISL-NEXT: std r3, -16(r1)2277; CHECK-FISL-NEXT: addi r3, r1, -162278; CHECK-FISL-NEXT: lxvd2x v2, 0, r32279; CHECK-FISL-NEXT: xvcvsxddp v2, v22280; CHECK-FISL-NEXT: blr2281;2282; CHECK-LE-LABEL: test69:2283; CHECK-LE: # %bb.0:2284; CHECK-LE-NEXT: addis r3, r2, .LCPI63_0@toc@ha2285; CHECK-LE-NEXT: addi r3, r3, .LCPI63_0@toc@l2286; CHECK-LE-NEXT: lxvd2x vs0, 0, r32287; CHECK-LE-NEXT: addis r3, r2, .LCPI63_1@toc@ha2288; CHECK-LE-NEXT: addi r3, r3, .LCPI63_1@toc@l2289; CHECK-LE-NEXT: xxswapd v3, vs02290; CHECK-LE-NEXT: vperm v2, v2, v2, v32291; CHECK-LE-NEXT: lxvd2x v3, 0, r32292; CHECK-LE-NEXT: vsld v2, v2, v32293; CHECK-LE-NEXT: vsrad v2, v2, v32294; CHECK-LE-NEXT: xvcvsxddp v2, v22295; CHECK-LE-NEXT: blr2296 %w = sitofp <2 x i16> %a to <2 x double>2297 ret <2 x double> %w2298 2299 2300}2301 2302; This gets scalarized so the code isn't great2303define <2 x double> @test70(<2 x i8> %a) {2304; CHECK-LABEL: test70:2305; CHECK: # %bb.0:2306; CHECK-NEXT: addis r3, r2, .LCPI64_0@toc@ha2307; CHECK-NEXT: addi r3, r3, .LCPI64_0@toc@l2308; CHECK-NEXT: lxvw4x v3, 0, r32309; CHECK-NEXT: addi r3, r1, -322310; CHECK-NEXT: vperm v2, v2, v2, v32311; CHECK-NEXT: stxvd2x v2, 0, r32312; CHECK-NEXT: ld r3, -24(r1)2313; CHECK-NEXT: extsb r3, r32314; CHECK-NEXT: std r3, -8(r1)2315; CHECK-NEXT: ld r3, -32(r1)2316; CHECK-NEXT: extsb r3, r32317; CHECK-NEXT: std r3, -16(r1)2318; CHECK-NEXT: addi r3, r1, -162319; CHECK-NEXT: lxvd2x v2, 0, r32320; CHECK-NEXT: xvcvsxddp v2, v22321; CHECK-NEXT: blr2322;2323; CHECK-REG-LABEL: test70:2324; CHECK-REG: # %bb.0:2325; CHECK-REG-NEXT: addis r3, r2, .LCPI64_0@toc@ha2326; CHECK-REG-NEXT: addi r3, r3, .LCPI64_0@toc@l2327; CHECK-REG-NEXT: lxvw4x v3, 0, r32328; CHECK-REG-NEXT: addi r3, r1, -322329; CHECK-REG-NEXT: vperm v2, v2, v2, v32330; CHECK-REG-NEXT: stxvd2x v2, 0, r32331; CHECK-REG-NEXT: ld r3, -24(r1)2332; CHECK-REG-NEXT: extsb r3, r32333; CHECK-REG-NEXT: std r3, -8(r1)2334; CHECK-REG-NEXT: ld r3, -32(r1)2335; CHECK-REG-NEXT: extsb r3, r32336; CHECK-REG-NEXT: std r3, -16(r1)2337; CHECK-REG-NEXT: addi r3, r1, -162338; CHECK-REG-NEXT: lxvd2x v2, 0, r32339; CHECK-REG-NEXT: xvcvsxddp v2, v22340; CHECK-REG-NEXT: blr2341;2342; CHECK-FISL-LABEL: test70:2343; CHECK-FISL: # %bb.0:2344; CHECK-FISL-NEXT: addis r3, r2, .LCPI64_0@toc@ha2345; CHECK-FISL-NEXT: addi r3, r3, .LCPI64_0@toc@l2346; CHECK-FISL-NEXT: lxvw4x v3, 0, r32347; CHECK-FISL-NEXT: vperm v2, v2, v2, v32348; CHECK-FISL-NEXT: xxlor vs0, v2, v22349; CHECK-FISL-NEXT: addi r3, r1, -322350; CHECK-FISL-NEXT: stxvd2x vs0, 0, r32351; CHECK-FISL-NEXT: ld r3, -24(r1)2352; CHECK-FISL-NEXT: extsb r3, r32353; CHECK-FISL-NEXT: std r3, -8(r1)2354; CHECK-FISL-NEXT: ld r3, -32(r1)2355; CHECK-FISL-NEXT: extsb r3, r32356; CHECK-FISL-NEXT: std r3, -16(r1)2357; CHECK-FISL-NEXT: addi r3, r1, -162358; CHECK-FISL-NEXT: lxvd2x v2, 0, r32359; CHECK-FISL-NEXT: xvcvsxddp v2, v22360; CHECK-FISL-NEXT: blr2361;2362; CHECK-LE-LABEL: test70:2363; CHECK-LE: # %bb.0:2364; CHECK-LE-NEXT: addis r3, r2, .LCPI64_0@toc@ha2365; CHECK-LE-NEXT: addi r3, r3, .LCPI64_0@toc@l2366; CHECK-LE-NEXT: lxvd2x vs0, 0, r32367; CHECK-LE-NEXT: addis r3, r2, .LCPI64_1@toc@ha2368; CHECK-LE-NEXT: addi r3, r3, .LCPI64_1@toc@l2369; CHECK-LE-NEXT: xxswapd v3, vs02370; CHECK-LE-NEXT: vperm v2, v2, v2, v32371; CHECK-LE-NEXT: lxvd2x v3, 0, r32372; CHECK-LE-NEXT: vsld v2, v2, v32373; CHECK-LE-NEXT: vsrad v2, v2, v32374; CHECK-LE-NEXT: xvcvsxddp v2, v22375; CHECK-LE-NEXT: blr2376 %w = sitofp <2 x i8> %a to <2 x double>2377 ret <2 x double> %w2378 2379 2380}2381 2382; This gets scalarized so the code isn't great2383define <2 x i32> @test80(i32 %v) {2384; CHECK-LABEL: test80:2385; CHECK: # %bb.0:2386; CHECK-NEXT: sldi r3, r3, 322387; CHECK-NEXT: std r3, -16(r1)2388; CHECK-NEXT: std r3, -8(r1)2389; CHECK-NEXT: addi r3, r1, -162390; CHECK-NEXT: lxvw4x vs0, 0, r32391; CHECK-NEXT: addis r3, r2, .LCPI65_0@toc@ha2392; CHECK-NEXT: addi r3, r3, .LCPI65_0@toc@l2393; CHECK-NEXT: lxvw4x v3, 0, r32394; CHECK-NEXT: xxspltw v2, vs0, 02395; CHECK-NEXT: vadduwm v2, v2, v32396; CHECK-NEXT: blr2397;2398; CHECK-REG-LABEL: test80:2399; CHECK-REG: # %bb.0:2400; CHECK-REG-NEXT: sldi r3, r3, 322401; CHECK-REG-NEXT: std r3, -16(r1)2402; CHECK-REG-NEXT: std r3, -8(r1)2403; CHECK-REG-NEXT: addi r3, r1, -162404; CHECK-REG-NEXT: lxvw4x vs0, 0, r32405; CHECK-REG-NEXT: addis r3, r2, .LCPI65_0@toc@ha2406; CHECK-REG-NEXT: addi r3, r3, .LCPI65_0@toc@l2407; CHECK-REG-NEXT: lxvw4x v3, 0, r32408; CHECK-REG-NEXT: xxspltw v2, vs0, 02409; CHECK-REG-NEXT: vadduwm v2, v2, v32410; CHECK-REG-NEXT: blr2411;2412; CHECK-FISL-LABEL: test80:2413; CHECK-FISL: # %bb.0:2414; CHECK-FISL-NEXT: mr r4, r32415; CHECK-FISL-NEXT: # implicit-def: $x32416; CHECK-FISL-NEXT: mr r3, r42417; CHECK-FISL-NEXT: sldi r3, r3, 322418; CHECK-FISL-NEXT: std r3, -8(r1)2419; CHECK-FISL-NEXT: std r3, -16(r1)2420; CHECK-FISL-NEXT: addi r3, r1, -162421; CHECK-FISL-NEXT: lxvw4x vs0, 0, r32422; CHECK-FISL-NEXT: xxspltw v2, vs0, 02423; CHECK-FISL-NEXT: addis r3, r2, .LCPI65_0@toc@ha2424; CHECK-FISL-NEXT: addi r3, r3, .LCPI65_0@toc@l2425; CHECK-FISL-NEXT: lxvw4x v3, 0, r32426; CHECK-FISL-NEXT: vadduwm v2, v2, v32427; CHECK-FISL-NEXT: blr2428;2429; CHECK-LE-LABEL: test80:2430; CHECK-LE: # %bb.0:2431; CHECK-LE-NEXT: mtfprwz f0, r32432; CHECK-LE-NEXT: addis r3, r2, .LCPI65_0@toc@ha2433; CHECK-LE-NEXT: addi r3, r3, .LCPI65_0@toc@l2434; CHECK-LE-NEXT: xxspltw v2, vs0, 12435; CHECK-LE-NEXT: lxvd2x vs0, 0, r32436; CHECK-LE-NEXT: xxswapd v3, vs02437; CHECK-LE-NEXT: vadduwm v2, v2, v32438; CHECK-LE-NEXT: blr2439 %b1 = insertelement <2 x i32> undef, i32 %v, i32 02440 %b2 = shufflevector <2 x i32> %b1, <2 x i32> undef, <2 x i32> zeroinitializer2441 %i = add <2 x i32> %b2, <i32 2, i32 3>2442 ret <2 x i32> %i2443 2444 2445 2446}2447 2448define <2 x double> @test81(<4 x float> %b) {2449; CHECK-LABEL: test81:2450; CHECK: # %bb.0:2451; CHECK-NEXT: blr2452;2453; CHECK-REG-LABEL: test81:2454; CHECK-REG: # %bb.0:2455; CHECK-REG-NEXT: blr2456;2457; CHECK-FISL-LABEL: test81:2458; CHECK-FISL: # %bb.0:2459; CHECK-FISL-NEXT: blr2460;2461; CHECK-LE-LABEL: test81:2462; CHECK-LE: # %bb.0:2463; CHECK-LE-NEXT: blr2464 %w = bitcast <4 x float> %b to <2 x double>2465 ret <2 x double> %w2466 2467 2468}2469 2470define double @test82(double %a, double %b, double %c, double %d) {2471; CHECK-LABEL: test82:2472; CHECK: # %bb.0: # %entry2473; CHECK-NEXT: xscmpudp cr0, f3, f42474; CHECK-NEXT: beqlr cr02475; CHECK-NEXT: # %bb.1: # %entry2476; CHECK-NEXT: fmr f1, f22477; CHECK-NEXT: blr2478;2479; CHECK-REG-LABEL: test82:2480; CHECK-REG: # %bb.0: # %entry2481; CHECK-REG-NEXT: xscmpudp cr0, f3, f42482; CHECK-REG-NEXT: beqlr cr02483; CHECK-REG-NEXT: # %bb.1: # %entry2484; CHECK-REG-NEXT: fmr f1, f22485; CHECK-REG-NEXT: blr2486;2487; CHECK-FISL-LABEL: test82:2488; CHECK-FISL: # %bb.0: # %entry2489; CHECK-FISL-NEXT: stfd f2, -16(r1) # 8-byte Folded Spill2490; CHECK-FISL-NEXT: fmr f2, f12491; CHECK-FISL-NEXT: xscmpudp cr0, f3, f42492; CHECK-FISL-NEXT: stfd f2, -8(r1) # 8-byte Folded Spill2493; CHECK-FISL-NEXT: beq cr0, .LBB67_22494; CHECK-FISL-NEXT: # %bb.1: # %entry2495; CHECK-FISL-NEXT: lfd f0, -16(r1) # 8-byte Folded Reload2496; CHECK-FISL-NEXT: stfd f0, -8(r1) # 8-byte Folded Spill2497; CHECK-FISL-NEXT: .LBB67_2: # %entry2498; CHECK-FISL-NEXT: lfd f1, -8(r1) # 8-byte Folded Reload2499; CHECK-FISL-NEXT: blr2500;2501; CHECK-LE-LABEL: test82:2502; CHECK-LE: # %bb.0: # %entry2503; CHECK-LE-NEXT: xscmpudp cr0, f3, f42504; CHECK-LE-NEXT: beqlr cr02505; CHECK-LE-NEXT: # %bb.1: # %entry2506; CHECK-LE-NEXT: fmr f1, f22507; CHECK-LE-NEXT: blr2508entry:2509 %m = fcmp oeq double %c, %d2510 %v = select i1 %m, double %a, double %b2511 ret double %v2512 2513 2514 2515}2516