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1; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck -check-prefix=CHECK-PWR9 %s3 4define <4 x i32> @testSpill(<4 x i32> %a, <4 x i32> %b) {5 6; CHECK-LABEL: testSpill:7; CHECK-DAG: li [[REG48:[0-9]+]], 488; CHECK-DAG: li [[REG64:[0-9]+]], 649; CHECK-DAG: li [[REG80:[0-9]+]], 8010; CHECK-DAG: li [[REG96:[0-9]+]], 9611; CHECK-DAG: stvx 28, 1, [[REG48]] # 16-byte Folded Spill12; CHECK-DAG: stvx 29, 1, [[REG64]] # 16-byte Folded Spill13; CHECK-DAG: stvx 30, 1, [[REG80]] # 16-byte Folded Spill14; CHECK-DAG: stvx 31, 1, [[REG96]] # 16-byte Folded Spill15; CHECK: .LBB0_316; CHECK-DAG: li [[REG96_LD:[0-9]+]], 9617; CHECK-DAG: li [[REG80_LD:[0-9]+]], 8018; CHECK-DAG: li [[REG64_LD:[0-9]+]], 6419; CHECK-DAG: li [[REG48_LD:[0-9]+]], 4820; CHECK-DAG: lvx 31, 1, [[REG96_LD]] # 16-byte Folded Reload21; CHECK-DAG: lvx 30, 1, [[REG80_LD]] # 16-byte Folded Reload22; CHECK-DAG: lvx 29, 1, [[REG64_LD]] # 16-byte Folded Reload23; CHECK-DAG: lvx 28, 1, [[REG48_LD]] # 16-byte Folded Reload24; CHECK: mtlr 025; CHECK-NEXT: blr26;27; CHECK-PWR9-LABEL: testSpill:28; CHECK-PWR9-DAG: stxv 62, 64(1) # 16-byte Folded Spill29; CHECK-PWR9-DAG: stxv 63, 80(1) # 16-byte Folded Spill30; CHECK-PWR9-DAG: stxv 60, 32(1) # 16-byte Folded Spill31; CHECK-PWR9-DAG: stxv 61, 48(1) # 16-byte Folded Spill32; CHECK-PWR9-NOT: NOT33; CHECK-PWR9-DAG: lxv 63, 80(1) # 16-byte Folded Reload34; CHECK-PWR9-DAG: lxv 62, 64(1) # 16-byte Folded Reload35; CHECK-PWR9-DAG: lxv 61, 48(1) # 16-byte Folded Reload36; CHECK-PWR9-DAG: lxv 60, 32(1) # 16-byte Folded Reload37; CHECK-PWR9: mtlr 038; CHECK-PWR9-NEXT: blr39 40entry:41 %0 = tail call i32 @llvm.ppc.altivec.vcmpgtsw.p(i32 2, <4 x i32> %a, <4 x i32> %b)42 %tobool = icmp eq i32 %0, 043 br i1 %tobool, label %if.else, label %if.then44 45if.then: ; preds = %entry46 %call = tail call <4 x i32> @test1(<4 x i32> %a, <4 x i32> %b)47 br label %if.end48 49if.else: ; preds = %entry50 %call1 = tail call <4 x i32> @test2(<4 x i32> %b, <4 x i32> %a)51 br label %if.end52 53if.end: ; preds = %if.else, %if.then54 %c.0.in = phi <4 x i32> [ %call, %if.then ], [ %call1, %if.else ]55 %call3 = tail call <4 x i32> @test1(<4 x i32> %b, <4 x i32> %a)56 %call5 = tail call <4 x i32> @test2(<4 x i32> %a, <4 x i32> %b)57 %add4 = add <4 x i32> %a, <i32 0, i32 0, i32 2, i32 2>58 %add6 = add <4 x i32> %add4, %c.0.in59 %c.0 = add <4 x i32> %add6, %call360 %add7 = add <4 x i32> %c.0, %call561 ret <4 x i32> %add762}63 64; Function Attrs: nounwind readnone65declare i32 @llvm.ppc.altivec.vcmpgtsw.p(i32, <4 x i32>, <4 x i32>)66declare <4 x i32> @test1(<4 x i32>, <4 x i32>)67declare <4 x i32> @test2(<4 x i32>, <4 x i32>)68