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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr9 \3; RUN: -mtriple=powerpc64le-unknown-linux-gnu \4; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \5; RUN: --check-prefixes=CHECK,CHECK-P9UP6; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=-power9-vector \7; RUN: -mtriple=powerpc64le-unknown-linux-gnu \8; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \9; RUN: --check-prefixes=CHECK,CHECK-NOINTRIN10; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+vsx \11; RUN: -mtriple=powerpc64le-unknown-linux-gnu \12; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \13; RUN: --check-prefixes=CHECK,CHECK-NOINTRIN14; RUN: llc -verify-machineinstrs -mcpu=pwr9 \15; RUN: -mtriple=powerpc64-unknown-linux-gnu \16; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \17; RUN: --check-prefixes=CHECK,CHECK-P9UP18; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=-power9-vector \19; RUN: -mtriple=powerpc64-unknown-linux-gnu \20; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \21; RUN: --check-prefixes=CHECK,CHECK-INTRIN22; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+vsx \23; RUN: -mtriple=powerpc64-unknown-linux-gnu \24; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \25; RUN: --check-prefixes=CHECK,CHECK-INTRIN26; RUN: llc -verify-machineinstrs -mcpu=pwr10 \27; RUN: -mtriple=powerpc64-unknown-linux-gnu \28; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \29; RUN: --check-prefixes=CHECK,CHECK-P9UP30; RUN: llc -verify-machineinstrs -mcpu=pwr10 \31; RUN: -mtriple=powerpc64le-unknown-linux-gnu \32; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \33; RUN: --check-prefixes=CHECK,CHECK-P9UP34 35; Function Attrs: nounwind readnone36define <4 x i32> @test1(ptr %a) {37; CHECK-LABEL: test1:38; CHECK: # %bb.0: # %entry39; CHECK-NEXT: lxvw4x v2, 0, r340; CHECK-NEXT: blr41 entry:42 %0 = tail call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(ptr %a)43 ret <4 x i32> %044}45; Function Attrs: nounwind readnone46declare <4 x i32> @llvm.ppc.vsx.lxvw4x.be(ptr)47 48; Function Attrs: nounwind readnone49define <2 x double> @test2(ptr %a) {50; CHECK-LABEL: test2:51; CHECK: # %bb.0: # %entry52; CHECK-NEXT: lxvd2x v2, 0, r353; CHECK-NEXT: blr54 entry:55 %0 = tail call <2 x double> @llvm.ppc.vsx.lxvd2x.be(ptr %a)56 ret <2 x double> %057}58; Function Attrs: nounwind readnone59declare <2 x double> @llvm.ppc.vsx.lxvd2x.be(ptr)60 61; Function Attrs: nounwind readnone62define void @test3(<4 x i32> %a, ptr %b) {63; CHECK-LABEL: test3:64; CHECK: # %bb.0: # %entry65; CHECK-NEXT: stxvw4x v2, 0, r566; CHECK-NEXT: blr67 entry:68 tail call void @llvm.ppc.vsx.stxvw4x.be(<4 x i32> %a, ptr %b)69 ret void70}71; Function Attrs: nounwind readnone72declare void @llvm.ppc.vsx.stxvw4x.be(<4 x i32>, ptr)73 74; Function Attrs: nounwind readnone75define void @test4(<2 x double> %a, ptr %b) {76; CHECK-LABEL: test4:77; CHECK: # %bb.0: # %entry78; CHECK-NEXT: stxvd2x v2, 0, r579; CHECK-NEXT: blr80 entry:81 tail call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %a, ptr %b)82 ret void83}84; Function Attrs: nounwind readnone85declare void @llvm.ppc.vsx.stxvd2x.be(<2 x double>, ptr)86 87define i32 @test_vec_test_swdiv(<2 x double> %a, <2 x double> %b) {88; CHECK-LABEL: test_vec_test_swdiv:89; CHECK: # %bb.0: # %entry90; CHECK-NEXT: xvtdivdp cr0, v2, v391; CHECK-NEXT: mfocrf r3, 12892; CHECK-NEXT: srwi r3, r3, 2893; CHECK-NEXT: blr94 entry:95 %0 = tail call i32 @llvm.ppc.vsx.xvtdivdp(<2 x double> %a, <2 x double> %b)96 ret i32 %097}98declare i32 @llvm.ppc.vsx.xvtdivdp(<2 x double>, <2 x double>)99 100define i32 @test_vec_test_swdivs(<4 x float> %a, <4 x float> %b) {101; CHECK-LABEL: test_vec_test_swdivs:102; CHECK: # %bb.0: # %entry103; CHECK-NEXT: xvtdivsp cr0, v2, v3104; CHECK-NEXT: mfocrf r3, 128105; CHECK-NEXT: srwi r3, r3, 28106; CHECK-NEXT: blr107 entry:108 %0 = tail call i32 @llvm.ppc.vsx.xvtdivsp(<4 x float> %a, <4 x float> %b)109 ret i32 %0110}111declare i32 @llvm.ppc.vsx.xvtdivsp(<4 x float>, <4 x float>)112 113define i32 @test_vec_test_swsqrt(<2 x double> %a) {114; CHECK-LABEL: test_vec_test_swsqrt:115; CHECK: # %bb.0: # %entry116; CHECK-NEXT: xvtsqrtdp cr0, v2117; CHECK-NEXT: mfocrf r3, 128118; CHECK-NEXT: srwi r3, r3, 28119; CHECK-NEXT: blr120 entry:121 %0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %a)122 ret i32 %0123}124declare i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double>)125 126define i32 @test_vec_test_swsqrts(<4 x float> %a) {127; CHECK-LABEL: test_vec_test_swsqrts:128; CHECK: # %bb.0: # %entry129; CHECK-NEXT: xvtsqrtsp cr0, v2130; CHECK-NEXT: mfocrf r3, 128131; CHECK-NEXT: srwi r3, r3, 28132; CHECK-NEXT: blr133 entry:134 %0 = tail call i32 @llvm.ppc.vsx.xvtsqrtsp(<4 x float> %a)135 ret i32 %0136}137declare i32 @llvm.ppc.vsx.xvtsqrtsp(<4 x float>)138 139define i32 @xvtdivdp_andi(<2 x double> %a, <2 x double> %b) {140; CHECK-LABEL: xvtdivdp_andi:141; CHECK: # %bb.0: # %entry142; CHECK-NEXT: xvtdivdp cr0, v2, v3143; CHECK-NEXT: li r4, 222144; CHECK-NEXT: mfocrf r3, 128145; CHECK-NEXT: srwi r3, r3, 28146; CHECK-NEXT: andi. r3, r3, 2147; CHECK-NEXT: li r3, 22148; CHECK-NEXT: iseleq r3, r4, r3149; CHECK-NEXT: blr150 entry:151 %0 = tail call i32 @llvm.ppc.vsx.xvtdivdp(<2 x double> %a, <2 x double> %b)152 %1 = and i32 %0, 2153 %cmp.not = icmp eq i32 %1, 0154 %retval.0 = select i1 %cmp.not, i32 222, i32 22155 ret i32 %retval.0156}157 158define i32 @xvtdivdp_shift(<2 x double> %a, <2 x double> %b) {159; CHECK-LABEL: xvtdivdp_shift:160; CHECK: # %bb.0: # %entry161; CHECK-NEXT: xvtdivdp cr0, v2, v3162; CHECK-NEXT: mfocrf r3, 128163; CHECK-NEXT: srwi r3, r3, 28164; CHECK-NEXT: rlwinm r3, r3, 28, 31, 31165; CHECK-NEXT: blr166entry:167 %0 = tail call i32 @llvm.ppc.vsx.xvtdivdp(<2 x double> %a, <2 x double> %b)168 %1 = lshr i32 %0, 4169 %.lobit = and i32 %1, 1170 ret i32 %.lobit171}172 173; Function Attrs: nounwind readnone174define <2 x double> @test_lxvd2x(ptr %a) {175; CHECK-P9UP-LABEL: test_lxvd2x:176; CHECK-P9UP: # %bb.0: # %entry177; CHECK-P9UP-NEXT: lxv v2, 0(r3)178; CHECK-P9UP-NEXT: blr179;180; CHECK-NOINTRIN-LABEL: test_lxvd2x:181; CHECK-NOINTRIN: # %bb.0: # %entry182; CHECK-NOINTRIN-NEXT: lxvd2x vs0, 0, r3183; CHECK-NOINTRIN-NEXT: xxswapd v2, vs0184; CHECK-NOINTRIN-NEXT: blr185;186; CHECK-INTRIN-LABEL: test_lxvd2x:187; CHECK-INTRIN: # %bb.0: # %entry188; CHECK-INTRIN-NEXT: lxvd2x v2, 0, r3189; CHECK-INTRIN-NEXT: blr190entry:191 %0 = tail call <2 x double> @llvm.ppc.vsx.lxvd2x(ptr %a)192 ret <2 x double> %0193}194; Function Attrs: nounwind readnone195declare <2 x double> @llvm.ppc.vsx.lxvd2x(ptr)196 197; Function Attrs: nounwind readnone198define void @test_stxvd2x(<2 x double> %a, ptr %b) {199; CHECK-P9UP-LABEL: test_stxvd2x:200; CHECK-P9UP: # %bb.0: # %entry201; CHECK-P9UP-NEXT: stxv v2, 0(r5)202; CHECK-P9UP-NEXT: blr203;204; CHECK-NOINTRIN-LABEL: test_stxvd2x:205; CHECK-NOINTRIN: # %bb.0: # %entry206; CHECK-NOINTRIN-NEXT: xxswapd vs0, v2207; CHECK-NOINTRIN-NEXT: stxvd2x vs0, 0, r5208; CHECK-NOINTRIN-NEXT: blr209;210; CHECK-INTRIN-LABEL: test_stxvd2x:211; CHECK-INTRIN: # %bb.0: # %entry212; CHECK-INTRIN-NEXT: stxvd2x v2, 0, r5213; CHECK-INTRIN-NEXT: blr214entry:215 tail call void @llvm.ppc.vsx.stxvd2x(<2 x double> %a, ptr %b)216 ret void217}218; Function Attrs: nounwind readnone219declare void @llvm.ppc.vsx.stxvd2x(<2 x double>, ptr)220