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1; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \2; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s3 4; Function Attrs: nounwind5; CHECK-LABEL: and_not6; CHECK: xxlandc v2, v2, v37; CHECK-NEXT: blr8define dso_local <4 x i32> @and_not(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {9entry:10 %neg = xor <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 -1>11 %and = and <4 x i32> %neg, %A12 ret <4 x i32> %and13}14 15; Function Attrs: nounwind16; CHECK-LABEL: and_and817; CHECK: xxeval v2, v3, v2, v4, 118; CHECK-NEXT: blr19define dso_local <16 x i8> @and_and8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C) local_unnamed_addr #0 {20entry:21 %and = and <16 x i8> %B, %A22 %and1 = and <16 x i8> %and, %C23 ret <16 x i8> %and124}25 26; Function Attrs: nounwind27; CHECK-LABEL: and_and1628; CHECK: xxeval v2, v3, v2, v4, 129; CHECK-NEXT: blr30define dso_local <8 x i16> @and_and16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C) local_unnamed_addr #0 {31entry:32 %and = and <8 x i16> %B, %A33 %and1 = and <8 x i16> %and, %C34 ret <8 x i16> %and135}36 37; Function Attrs: nounwind38; CHECK-LABEL: and_and3239; CHECK: xxeval v2, v3, v2, v4, 140; CHECK-NEXT: blr41define dso_local <4 x i32> @and_and32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {42entry:43 %and = and <4 x i32> %B, %A44 %and1 = and <4 x i32> %and, %C45 ret <4 x i32> %and146}47 48; Function Attrs: nounwind49; CHECK-LABEL: and_and6450; CHECK: xxeval v2, v3, v2, v4, 151; CHECK-NEXT: blr52define dso_local <2 x i64> @and_and64(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {53entry:54 %and = and <2 x i64> %B, %A55 %and1 = and <2 x i64> %and, %C56 ret <2 x i64> %and157}58 59; Function Attrs: nounwind60; CHECK-LABEL: and_nand61; CHECK: xxeval v2, v2, v4, v3, 1462; CHECK-NEXT: blr63define dso_local <4 x i32> @and_nand(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {64entry:65 %and = and <4 x i32> %C, %B66 %neg = xor <4 x i32> %and, <i32 -1, i32 -1, i32 -1, i32 -1>67 %and1 = and <4 x i32> %neg, %A68 ret <4 x i32> %and169}70 71; Function Attrs: nounwind72; CHECK-LABEL: and_or73; CHECK: xxeval v2, v2, v4, v3, 774; CHECK-NEXT: blr75define dso_local <4 x i32> @and_or(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {76entry:77 %or = or <4 x i32> %C, %B78 %and = and <4 x i32> %or, %A79 ret <4 x i32> %and80}81 82; Function Attrs: nounwind83; CHECK-LABEL: and_nor84; CHECK: xxeval v2, v2, v4, v3, 885; CHECK-NEXT: blr86define dso_local <4 x i32> @and_nor(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {87entry:88 %or = or <4 x i32> %C, %B89 %neg = xor <4 x i32> %or, <i32 -1, i32 -1, i32 -1, i32 -1>90 %and = and <4 x i32> %neg, %A91 ret <4 x i32> %and92}93 94; Function Attrs: nounwind95; CHECK-LABEL: and_xor96; CHECK: xxeval v2, v2, v4, v3, 697; CHECK-NEXT: blr98define dso_local <4 x i32> @and_xor(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {99entry:100 %xor = xor <4 x i32> %C, %B101 %and = and <4 x i32> %xor, %A102 ret <4 x i32> %and103}104 105; Function Attrs: nounwind106; CHECK-LABEL: and_eqv107; CHECK: xxeval v2, v2, v3, v4, 9108; CHECK-NEXT: blr109define dso_local <4 x i32> @and_eqv(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {110entry:111 %xor = xor <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 -1>112 %neg = xor <4 x i32> %xor, %C113 %and = and <4 x i32> %neg, %A114 ret <4 x i32> %and115}116 117; Function Attrs: nounwind118; CHECK-LABEL: nand_nand119; CHECK: xxeval v2, v2, v4, v3, 241120; CHECK-NEXT: blr121define dso_local <4 x i32> @nand_nand(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {122entry:123 %and = and <4 x i32> %C, %B124 %A.not = xor <4 x i32> %A, <i32 -1, i32 -1, i32 -1, i32 -1>125 %neg2 = or <4 x i32> %and, %A.not126 ret <4 x i32> %neg2127}128 129; Function Attrs: nounwind130; CHECK-LABEL: nand_and131; CHECK: xxeval v2, v3, v2, v4, 254132; CHECK-NEXT: blr133define dso_local <4 x i32> @nand_and(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {134entry:135 %and = and <4 x i32> %B, %A136 %and1 = and <4 x i32> %and, %C137 %neg = xor <4 x i32> %and1, <i32 -1, i32 -1, i32 -1, i32 -1>138 ret <4 x i32> %neg139}140 141; Function Attrs: nounwind142; CHECK-LABEL: nand_xor143; CHECK: xxeval v2, v2, v4, v3, 249144; CHECK-NEXT: blr145define dso_local <4 x i32> @nand_xor(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {146entry:147 %xor = xor <4 x i32> %C, %B148 %and = and <4 x i32> %xor, %A149 %neg = xor <4 x i32> %and, <i32 -1, i32 -1, i32 -1, i32 -1>150 ret <4 x i32> %neg151}152 153; Function Attrs: nounwind154; CHECK-LABEL: nand_eqv155; CHECK: xxeval v2, v2, v4, v3, 246156; CHECK-NEXT: blr157define dso_local <4 x i32> @nand_eqv(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {158entry:159 %xor = xor <4 x i32> %C, %B160 %A.not = xor <4 x i32> %A, <i32 -1, i32 -1, i32 -1, i32 -1>161 %neg1 = or <4 x i32> %xor, %A.not162 ret <4 x i32> %neg1163}164 165; Function Attrs: nounwind166; CHECK-LABEL: nand_or167; CHECK: xxeval v2, v2, v4, v3, 248168; CHECK-NEXT: blr169define dso_local <4 x i32> @nand_or(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {170entry:171 %or = or <4 x i32> %C, %B172 %and = and <4 x i32> %or, %A173 %neg = xor <4 x i32> %and, <i32 -1, i32 -1, i32 -1, i32 -1>174 ret <4 x i32> %neg175}176 177; Function Attrs: nounwind178; CHECK-LABEL: nand_nor179; CHECK: xxeval v2, v2, v3, v4, 247180; CHECK-NEXT: blr181define dso_local <4 x i32> @nand_nor(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {182entry:183 %A.not = xor <4 x i32> %A, <i32 -1, i32 -1, i32 -1, i32 -1>184 %or = or <4 x i32> %A.not, %B185 %neg1 = or <4 x i32> %or, %C186 ret <4 x i32> %neg1187}188 189attributes #0 = { nounwind }190