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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+m -global-isel -verify-machineinstrs < %s \3; RUN: | FileCheck %s --check-prefix=RV64IM4 5define i64 @sll_i64(i64 %a, i64 %b) {6; RV64IM-LABEL: sll_i64:7; RV64IM: # %bb.0: # %entry8; RV64IM-NEXT: sll a0, a0, a19; RV64IM-NEXT: ret10entry:11 %0 = shl i64 %a, %b12 ret i64 %013}14 15define i64 @slli_i64(i64 %a) {16; RV64IM-LABEL: slli_i64:17; RV64IM: # %bb.0: # %entry18; RV64IM-NEXT: slli a0, a0, 3319; RV64IM-NEXT: ret20entry:21 %0 = shl i64 %a, 3322 ret i64 %023}24 25define i64 @sra_i64(i64 %a, i64 %b) {26; RV64IM-LABEL: sra_i64:27; RV64IM: # %bb.0: # %entry28; RV64IM-NEXT: sra a0, a0, a129; RV64IM-NEXT: ret30entry:31 %0 = ashr i64 %a, %b32 ret i64 %033}34 35define i64 @srai_i64(i64 %a) {36; RV64IM-LABEL: srai_i64:37; RV64IM: # %bb.0: # %entry38; RV64IM-NEXT: srai a0, a0, 4739; RV64IM-NEXT: ret40entry:41 %0 = ashr i64 %a, 4742 ret i64 %043}44 45define i64 @srl_i64(i64 %a, i64 %b) {46; RV64IM-LABEL: srl_i64:47; RV64IM: # %bb.0: # %entry48; RV64IM-NEXT: srl a0, a0, a149; RV64IM-NEXT: ret50entry:51 %0 = lshr i64 %a, %b52 ret i64 %053}54 55define i64 @srli_i64(i64 %a, i64 %b) {56; RV64IM-LABEL: srli_i64:57; RV64IM: # %bb.0: # %entry58; RV64IM-NEXT: srli a0, a0, 5559; RV64IM-NEXT: ret60entry:61 %0 = lshr i64 %a, 5562 ret i64 %063}64 65define i64 @sdiv_i64(i64 %a, i64 %b) {66; RV64IM-LABEL: sdiv_i64:67; RV64IM: # %bb.0: # %entry68; RV64IM-NEXT: div a0, a0, a169; RV64IM-NEXT: ret70entry:71 %0 = sdiv i64 %a, %b72 ret i64 %073}74 75define i64 @srem_i64(i64 %a, i64 %b) {76; RV64IM-LABEL: srem_i64:77; RV64IM: # %bb.0: # %entry78; RV64IM-NEXT: rem a0, a0, a179; RV64IM-NEXT: ret80entry:81 %0 = srem i64 %a, %b82 ret i64 %083}84 85define i64 @udiv_i64(i64 %a, i64 %b) {86; RV64IM-LABEL: udiv_i64:87; RV64IM: # %bb.0: # %entry88; RV64IM-NEXT: divu a0, a0, a189; RV64IM-NEXT: ret90entry:91 %0 = udiv i64 %a, %b92 ret i64 %093}94 95define i64 @urem_i64(i64 %a, i64 %b) {96; RV64IM-LABEL: urem_i64:97; RV64IM: # %bb.0: # %entry98; RV64IM-NEXT: remu a0, a0, a199; RV64IM-NEXT: ret100entry:101 %0 = urem i64 %a, %b102 ret i64 %0103}104 105define i64 @zext_nneg_i32_i64(i32 %a) {106; RV64IM-LABEL: zext_nneg_i32_i64:107; RV64IM: # %bb.0: # %entry108; RV64IM-NEXT: sext.w a0, a0109; RV64IM-NEXT: ret110entry:111 %b = zext nneg i32 %a to i64112 ret i64 %b113}114