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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=riscv32 -global-isel -verify-machineinstrs < %s \3; RUN: | FileCheck %s --check-prefixes=RV32I4; RUN: llc -mtriple=riscv32 -global-isel -mattr=+zbb -verify-machineinstrs < %s \5; RUN: | FileCheck %s --check-prefixes=RV32ZBB6; RUN: llc -mtriple=riscv64 -global-isel -verify-machineinstrs < %s \7; RUN: | FileCheck %s --check-prefixes=RV64I8; RUN: llc -mtriple=riscv64 -global-isel -mattr=+zbb -verify-machineinstrs < %s \9; RUN: | FileCheck %s --check-prefixes=RV64ZBB10 11define i32 @expanded_neg_abs32(i32 %x) {12; RV32I-LABEL: expanded_neg_abs32:13; RV32I: # %bb.0:14; RV32I-NEXT: neg a1, a015; RV32I-NEXT: blt a0, a1, .LBB0_216; RV32I-NEXT: # %bb.1:17; RV32I-NEXT: mv a1, a018; RV32I-NEXT: .LBB0_2:19; RV32I-NEXT: neg a0, a120; RV32I-NEXT: ret21;22; RV32ZBB-LABEL: expanded_neg_abs32:23; RV32ZBB: # %bb.0:24; RV32ZBB-NEXT: neg a1, a025; RV32ZBB-NEXT: min a0, a0, a126; RV32ZBB-NEXT: ret27;28; RV64I-LABEL: expanded_neg_abs32:29; RV64I: # %bb.0:30; RV64I-NEXT: negw a1, a031; RV64I-NEXT: sext.w a2, a032; RV64I-NEXT: blt a2, a1, .LBB0_233; RV64I-NEXT: # %bb.1:34; RV64I-NEXT: mv a1, a035; RV64I-NEXT: .LBB0_2:36; RV64I-NEXT: negw a0, a137; RV64I-NEXT: ret38;39; RV64ZBB-LABEL: expanded_neg_abs32:40; RV64ZBB: # %bb.0:41; RV64ZBB-NEXT: negw a1, a042; RV64ZBB-NEXT: sext.w a0, a043; RV64ZBB-NEXT: max a0, a1, a044; RV64ZBB-NEXT: negw a0, a045; RV64ZBB-NEXT: ret46 %n = sub i32 0, %x47 %t = call i32 @llvm.smax.i32(i32 %n, i32 %x)48 %r = sub i32 0, %t49 ret i32 %r50}51 52define i32 @expanded_neg_abs32_unsigned(i32 %x) {53; RV32I-LABEL: expanded_neg_abs32_unsigned:54; RV32I: # %bb.0:55; RV32I-NEXT: neg a1, a056; RV32I-NEXT: bltu a0, a1, .LBB1_257; RV32I-NEXT: # %bb.1:58; RV32I-NEXT: mv a1, a059; RV32I-NEXT: .LBB1_2:60; RV32I-NEXT: neg a0, a161; RV32I-NEXT: ret62;63; RV32ZBB-LABEL: expanded_neg_abs32_unsigned:64; RV32ZBB: # %bb.0:65; RV32ZBB-NEXT: neg a1, a066; RV32ZBB-NEXT: minu a0, a0, a167; RV32ZBB-NEXT: ret68;69; RV64I-LABEL: expanded_neg_abs32_unsigned:70; RV64I: # %bb.0:71; RV64I-NEXT: negw a1, a072; RV64I-NEXT: sext.w a2, a073; RV64I-NEXT: bltu a2, a1, .LBB1_274; RV64I-NEXT: # %bb.1:75; RV64I-NEXT: mv a1, a076; RV64I-NEXT: .LBB1_2:77; RV64I-NEXT: negw a0, a178; RV64I-NEXT: ret79;80; RV64ZBB-LABEL: expanded_neg_abs32_unsigned:81; RV64ZBB: # %bb.0:82; RV64ZBB-NEXT: negw a1, a083; RV64ZBB-NEXT: sext.w a0, a084; RV64ZBB-NEXT: maxu a0, a1, a085; RV64ZBB-NEXT: negw a0, a086; RV64ZBB-NEXT: ret87 %n = sub i32 0, %x88 %t = call i32 @llvm.umax.i32(i32 %n, i32 %x)89 %r = sub i32 0, %t90 ret i32 %r91}92 93define i64 @expanded_neg_abs64(i64 %x) {94; RV32I-LABEL: expanded_neg_abs64:95; RV32I: # %bb.0:96; RV32I-NEXT: snez a2, a097; RV32I-NEXT: neg a3, a198; RV32I-NEXT: sub a2, a3, a299; RV32I-NEXT: neg a3, a0100; RV32I-NEXT: beq a2, a1, .LBB2_2101; RV32I-NEXT: # %bb.1:102; RV32I-NEXT: slt a4, a1, a2103; RV32I-NEXT: beqz a4, .LBB2_3104; RV32I-NEXT: j .LBB2_4105; RV32I-NEXT: .LBB2_2:106; RV32I-NEXT: sltu a4, a0, a3107; RV32I-NEXT: bnez a4, .LBB2_4108; RV32I-NEXT: .LBB2_3:109; RV32I-NEXT: mv a3, a0110; RV32I-NEXT: mv a2, a1111; RV32I-NEXT: .LBB2_4:112; RV32I-NEXT: neg a0, a3113; RV32I-NEXT: snez a1, a3114; RV32I-NEXT: neg a2, a2115; RV32I-NEXT: sub a1, a2, a1116; RV32I-NEXT: ret117;118; RV32ZBB-LABEL: expanded_neg_abs64:119; RV32ZBB: # %bb.0:120; RV32ZBB-NEXT: snez a2, a0121; RV32ZBB-NEXT: neg a3, a1122; RV32ZBB-NEXT: sub a2, a3, a2123; RV32ZBB-NEXT: neg a3, a0124; RV32ZBB-NEXT: beq a2, a1, .LBB2_2125; RV32ZBB-NEXT: # %bb.1:126; RV32ZBB-NEXT: slt a4, a1, a2127; RV32ZBB-NEXT: beqz a4, .LBB2_3128; RV32ZBB-NEXT: j .LBB2_4129; RV32ZBB-NEXT: .LBB2_2:130; RV32ZBB-NEXT: sltu a4, a0, a3131; RV32ZBB-NEXT: bnez a4, .LBB2_4132; RV32ZBB-NEXT: .LBB2_3:133; RV32ZBB-NEXT: mv a3, a0134; RV32ZBB-NEXT: mv a2, a1135; RV32ZBB-NEXT: .LBB2_4:136; RV32ZBB-NEXT: neg a0, a3137; RV32ZBB-NEXT: snez a1, a3138; RV32ZBB-NEXT: neg a2, a2139; RV32ZBB-NEXT: sub a1, a2, a1140; RV32ZBB-NEXT: ret141;142; RV64I-LABEL: expanded_neg_abs64:143; RV64I: # %bb.0:144; RV64I-NEXT: neg a1, a0145; RV64I-NEXT: blt a0, a1, .LBB2_2146; RV64I-NEXT: # %bb.1:147; RV64I-NEXT: mv a1, a0148; RV64I-NEXT: .LBB2_2:149; RV64I-NEXT: neg a0, a1150; RV64I-NEXT: ret151;152; RV64ZBB-LABEL: expanded_neg_abs64:153; RV64ZBB: # %bb.0:154; RV64ZBB-NEXT: neg a1, a0155; RV64ZBB-NEXT: min a0, a0, a1156; RV64ZBB-NEXT: ret157 %n = sub i64 0, %x158 %t = call i64 @llvm.smax.i64(i64 %n, i64 %x)159 %r = sub i64 0, %t160 ret i64 %r161}162 163define i64 @expanded_neg_abs64_unsigned(i64 %x) {164; RV32I-LABEL: expanded_neg_abs64_unsigned:165; RV32I: # %bb.0:166; RV32I-NEXT: snez a2, a0167; RV32I-NEXT: neg a3, a1168; RV32I-NEXT: sub a2, a3, a2169; RV32I-NEXT: neg a3, a0170; RV32I-NEXT: beq a2, a1, .LBB3_2171; RV32I-NEXT: # %bb.1:172; RV32I-NEXT: sltu a4, a1, a2173; RV32I-NEXT: beqz a4, .LBB3_3174; RV32I-NEXT: j .LBB3_4175; RV32I-NEXT: .LBB3_2:176; RV32I-NEXT: sltu a4, a0, a3177; RV32I-NEXT: bnez a4, .LBB3_4178; RV32I-NEXT: .LBB3_3:179; RV32I-NEXT: mv a3, a0180; RV32I-NEXT: mv a2, a1181; RV32I-NEXT: .LBB3_4:182; RV32I-NEXT: neg a0, a3183; RV32I-NEXT: snez a1, a3184; RV32I-NEXT: neg a2, a2185; RV32I-NEXT: sub a1, a2, a1186; RV32I-NEXT: ret187;188; RV32ZBB-LABEL: expanded_neg_abs64_unsigned:189; RV32ZBB: # %bb.0:190; RV32ZBB-NEXT: snez a2, a0191; RV32ZBB-NEXT: neg a3, a1192; RV32ZBB-NEXT: sub a2, a3, a2193; RV32ZBB-NEXT: neg a3, a0194; RV32ZBB-NEXT: beq a2, a1, .LBB3_2195; RV32ZBB-NEXT: # %bb.1:196; RV32ZBB-NEXT: sltu a4, a1, a2197; RV32ZBB-NEXT: beqz a4, .LBB3_3198; RV32ZBB-NEXT: j .LBB3_4199; RV32ZBB-NEXT: .LBB3_2:200; RV32ZBB-NEXT: sltu a4, a0, a3201; RV32ZBB-NEXT: bnez a4, .LBB3_4202; RV32ZBB-NEXT: .LBB3_3:203; RV32ZBB-NEXT: mv a3, a0204; RV32ZBB-NEXT: mv a2, a1205; RV32ZBB-NEXT: .LBB3_4:206; RV32ZBB-NEXT: neg a0, a3207; RV32ZBB-NEXT: snez a1, a3208; RV32ZBB-NEXT: neg a2, a2209; RV32ZBB-NEXT: sub a1, a2, a1210; RV32ZBB-NEXT: ret211;212; RV64I-LABEL: expanded_neg_abs64_unsigned:213; RV64I: # %bb.0:214; RV64I-NEXT: neg a1, a0215; RV64I-NEXT: bltu a0, a1, .LBB3_2216; RV64I-NEXT: # %bb.1:217; RV64I-NEXT: mv a1, a0218; RV64I-NEXT: .LBB3_2:219; RV64I-NEXT: neg a0, a1220; RV64I-NEXT: ret221;222; RV64ZBB-LABEL: expanded_neg_abs64_unsigned:223; RV64ZBB: # %bb.0:224; RV64ZBB-NEXT: neg a1, a0225; RV64ZBB-NEXT: minu a0, a0, a1226; RV64ZBB-NEXT: ret227 %n = sub i64 0, %x228 %t = call i64 @llvm.umax.i64(i64 %n, i64 %x)229 %r = sub i64 0, %t230 ret i64 %r231}232 233define i32 @expanded_neg_inv_abs32(i32 %x) {234; RV32I-LABEL: expanded_neg_inv_abs32:235; RV32I: # %bb.0:236; RV32I-NEXT: neg a1, a0237; RV32I-NEXT: blt a1, a0, .LBB4_2238; RV32I-NEXT: # %bb.1:239; RV32I-NEXT: mv a1, a0240; RV32I-NEXT: .LBB4_2:241; RV32I-NEXT: neg a0, a1242; RV32I-NEXT: ret243;244; RV32ZBB-LABEL: expanded_neg_inv_abs32:245; RV32ZBB: # %bb.0:246; RV32ZBB-NEXT: neg a1, a0247; RV32ZBB-NEXT: max a0, a0, a1248; RV32ZBB-NEXT: ret249;250; RV64I-LABEL: expanded_neg_inv_abs32:251; RV64I: # %bb.0:252; RV64I-NEXT: negw a1, a0253; RV64I-NEXT: sext.w a2, a0254; RV64I-NEXT: blt a1, a2, .LBB4_2255; RV64I-NEXT: # %bb.1:256; RV64I-NEXT: mv a1, a0257; RV64I-NEXT: .LBB4_2:258; RV64I-NEXT: negw a0, a1259; RV64I-NEXT: ret260;261; RV64ZBB-LABEL: expanded_neg_inv_abs32:262; RV64ZBB: # %bb.0:263; RV64ZBB-NEXT: negw a1, a0264; RV64ZBB-NEXT: sext.w a0, a0265; RV64ZBB-NEXT: min a0, a1, a0266; RV64ZBB-NEXT: negw a0, a0267; RV64ZBB-NEXT: ret268 %n = sub i32 0, %x269 %t = call i32 @llvm.smin.i32(i32 %n, i32 %x)270 %r = sub i32 0, %t271 ret i32 %r272}273 274define i32 @expanded_neg_inv_abs32_unsigned(i32 %x) {275; RV32I-LABEL: expanded_neg_inv_abs32_unsigned:276; RV32I: # %bb.0:277; RV32I-NEXT: neg a1, a0278; RV32I-NEXT: bltu a1, a0, .LBB5_2279; RV32I-NEXT: # %bb.1:280; RV32I-NEXT: mv a1, a0281; RV32I-NEXT: .LBB5_2:282; RV32I-NEXT: neg a0, a1283; RV32I-NEXT: ret284;285; RV32ZBB-LABEL: expanded_neg_inv_abs32_unsigned:286; RV32ZBB: # %bb.0:287; RV32ZBB-NEXT: neg a1, a0288; RV32ZBB-NEXT: maxu a0, a0, a1289; RV32ZBB-NEXT: ret290;291; RV64I-LABEL: expanded_neg_inv_abs32_unsigned:292; RV64I: # %bb.0:293; RV64I-NEXT: negw a1, a0294; RV64I-NEXT: sext.w a2, a0295; RV64I-NEXT: bltu a1, a2, .LBB5_2296; RV64I-NEXT: # %bb.1:297; RV64I-NEXT: mv a1, a0298; RV64I-NEXT: .LBB5_2:299; RV64I-NEXT: negw a0, a1300; RV64I-NEXT: ret301;302; RV64ZBB-LABEL: expanded_neg_inv_abs32_unsigned:303; RV64ZBB: # %bb.0:304; RV64ZBB-NEXT: negw a1, a0305; RV64ZBB-NEXT: sext.w a0, a0306; RV64ZBB-NEXT: minu a0, a1, a0307; RV64ZBB-NEXT: negw a0, a0308; RV64ZBB-NEXT: ret309 %n = sub i32 0, %x310 %t = call i32 @llvm.umin.i32(i32 %n, i32 %x)311 %r = sub i32 0, %t312 ret i32 %r313}314 315define i64 @expanded_neg_inv_abs64(i64 %x) {316; RV32I-LABEL: expanded_neg_inv_abs64:317; RV32I: # %bb.0:318; RV32I-NEXT: snez a2, a0319; RV32I-NEXT: neg a3, a1320; RV32I-NEXT: sub a2, a3, a2321; RV32I-NEXT: neg a3, a0322; RV32I-NEXT: beq a2, a1, .LBB6_2323; RV32I-NEXT: # %bb.1:324; RV32I-NEXT: slt a4, a2, a1325; RV32I-NEXT: beqz a4, .LBB6_3326; RV32I-NEXT: j .LBB6_4327; RV32I-NEXT: .LBB6_2:328; RV32I-NEXT: sltu a4, a3, a0329; RV32I-NEXT: bnez a4, .LBB6_4330; RV32I-NEXT: .LBB6_3:331; RV32I-NEXT: mv a3, a0332; RV32I-NEXT: mv a2, a1333; RV32I-NEXT: .LBB6_4:334; RV32I-NEXT: neg a0, a3335; RV32I-NEXT: snez a1, a3336; RV32I-NEXT: neg a2, a2337; RV32I-NEXT: sub a1, a2, a1338; RV32I-NEXT: ret339;340; RV32ZBB-LABEL: expanded_neg_inv_abs64:341; RV32ZBB: # %bb.0:342; RV32ZBB-NEXT: snez a2, a0343; RV32ZBB-NEXT: neg a3, a1344; RV32ZBB-NEXT: sub a2, a3, a2345; RV32ZBB-NEXT: neg a3, a0346; RV32ZBB-NEXT: beq a2, a1, .LBB6_2347; RV32ZBB-NEXT: # %bb.1:348; RV32ZBB-NEXT: slt a4, a2, a1349; RV32ZBB-NEXT: beqz a4, .LBB6_3350; RV32ZBB-NEXT: j .LBB6_4351; RV32ZBB-NEXT: .LBB6_2:352; RV32ZBB-NEXT: sltu a4, a3, a0353; RV32ZBB-NEXT: bnez a4, .LBB6_4354; RV32ZBB-NEXT: .LBB6_3:355; RV32ZBB-NEXT: mv a3, a0356; RV32ZBB-NEXT: mv a2, a1357; RV32ZBB-NEXT: .LBB6_4:358; RV32ZBB-NEXT: neg a0, a3359; RV32ZBB-NEXT: snez a1, a3360; RV32ZBB-NEXT: neg a2, a2361; RV32ZBB-NEXT: sub a1, a2, a1362; RV32ZBB-NEXT: ret363;364; RV64I-LABEL: expanded_neg_inv_abs64:365; RV64I: # %bb.0:366; RV64I-NEXT: neg a1, a0367; RV64I-NEXT: blt a1, a0, .LBB6_2368; RV64I-NEXT: # %bb.1:369; RV64I-NEXT: mv a1, a0370; RV64I-NEXT: .LBB6_2:371; RV64I-NEXT: neg a0, a1372; RV64I-NEXT: ret373;374; RV64ZBB-LABEL: expanded_neg_inv_abs64:375; RV64ZBB: # %bb.0:376; RV64ZBB-NEXT: neg a1, a0377; RV64ZBB-NEXT: max a0, a0, a1378; RV64ZBB-NEXT: ret379 %n = sub i64 0, %x380 %t = call i64 @llvm.smin.i64(i64 %n, i64 %x)381 %r = sub i64 0, %t382 ret i64 %r383}384 385define i64 @expanded_neg_inv_abs64_unsigned(i64 %x) {386; RV32I-LABEL: expanded_neg_inv_abs64_unsigned:387; RV32I: # %bb.0:388; RV32I-NEXT: snez a2, a0389; RV32I-NEXT: neg a3, a1390; RV32I-NEXT: sub a2, a3, a2391; RV32I-NEXT: neg a3, a0392; RV32I-NEXT: beq a2, a1, .LBB7_2393; RV32I-NEXT: # %bb.1:394; RV32I-NEXT: sltu a4, a2, a1395; RV32I-NEXT: beqz a4, .LBB7_3396; RV32I-NEXT: j .LBB7_4397; RV32I-NEXT: .LBB7_2:398; RV32I-NEXT: sltu a4, a3, a0399; RV32I-NEXT: bnez a4, .LBB7_4400; RV32I-NEXT: .LBB7_3:401; RV32I-NEXT: mv a3, a0402; RV32I-NEXT: mv a2, a1403; RV32I-NEXT: .LBB7_4:404; RV32I-NEXT: neg a0, a3405; RV32I-NEXT: snez a1, a3406; RV32I-NEXT: neg a2, a2407; RV32I-NEXT: sub a1, a2, a1408; RV32I-NEXT: ret409;410; RV32ZBB-LABEL: expanded_neg_inv_abs64_unsigned:411; RV32ZBB: # %bb.0:412; RV32ZBB-NEXT: snez a2, a0413; RV32ZBB-NEXT: neg a3, a1414; RV32ZBB-NEXT: sub a2, a3, a2415; RV32ZBB-NEXT: neg a3, a0416; RV32ZBB-NEXT: beq a2, a1, .LBB7_2417; RV32ZBB-NEXT: # %bb.1:418; RV32ZBB-NEXT: sltu a4, a2, a1419; RV32ZBB-NEXT: beqz a4, .LBB7_3420; RV32ZBB-NEXT: j .LBB7_4421; RV32ZBB-NEXT: .LBB7_2:422; RV32ZBB-NEXT: sltu a4, a3, a0423; RV32ZBB-NEXT: bnez a4, .LBB7_4424; RV32ZBB-NEXT: .LBB7_3:425; RV32ZBB-NEXT: mv a3, a0426; RV32ZBB-NEXT: mv a2, a1427; RV32ZBB-NEXT: .LBB7_4:428; RV32ZBB-NEXT: neg a0, a3429; RV32ZBB-NEXT: snez a1, a3430; RV32ZBB-NEXT: neg a2, a2431; RV32ZBB-NEXT: sub a1, a2, a1432; RV32ZBB-NEXT: ret433;434; RV64I-LABEL: expanded_neg_inv_abs64_unsigned:435; RV64I: # %bb.0:436; RV64I-NEXT: neg a1, a0437; RV64I-NEXT: bltu a1, a0, .LBB7_2438; RV64I-NEXT: # %bb.1:439; RV64I-NEXT: mv a1, a0440; RV64I-NEXT: .LBB7_2:441; RV64I-NEXT: neg a0, a1442; RV64I-NEXT: ret443;444; RV64ZBB-LABEL: expanded_neg_inv_abs64_unsigned:445; RV64ZBB: # %bb.0:446; RV64ZBB-NEXT: neg a1, a0447; RV64ZBB-NEXT: maxu a0, a0, a1448; RV64ZBB-NEXT: ret449 %n = sub i64 0, %x450 %t = call i64 @llvm.umin.i64(i64 %n, i64 %x)451 %r = sub i64 0, %t452 ret i64 %r453}454