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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs -global-isel < %s \3; RUN: | FileCheck -check-prefixes=RV32,RV32IM %s4; RUN: llc -mtriple=riscv32 -mattr=+m,+zba,+zbb \5; RUN: -verify-machineinstrs -global-isel < %s \6; RUN: | FileCheck -check-prefixes=RV32,RV32IMZB %s7; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs -global-isel < %s \8; RUN: | FileCheck -check-prefixes=RV64,RV64IM %s9; RUN: llc -mtriple=riscv64 -mattr=+m,+zba,+zbb \10; RUN: -verify-machineinstrs -global-isel < %s \11; RUN: | FileCheck -check-prefixes=RV64,RV64IMZB %s12 13; Test that there is a single shift after the mul and no addition.14define i32 @udiv_constant_no_add(i32 %a) nounwind {15; RV32-LABEL: udiv_constant_no_add:16; RV32: # %bb.0:17; RV32-NEXT: lui a1, 83886118; RV32-NEXT: addi a1, a1, -81919; RV32-NEXT: mulhu a0, a0, a120; RV32-NEXT: srli a0, a0, 221; RV32-NEXT: ret22;23; RV64IM-LABEL: udiv_constant_no_add:24; RV64IM: # %bb.0:25; RV64IM-NEXT: slli a0, a0, 3226; RV64IM-NEXT: lui a1, 20527; RV64IM-NEXT: srli a0, a0, 3228; RV64IM-NEXT: addi a1, a1, -81929; RV64IM-NEXT: slli a1, a1, 1230; RV64IM-NEXT: addi a1, a1, -81931; RV64IM-NEXT: mul a0, a0, a132; RV64IM-NEXT: srli a0, a0, 3433; RV64IM-NEXT: ret34;35; RV64IMZB-LABEL: udiv_constant_no_add:36; RV64IMZB: # %bb.0:37; RV64IMZB-NEXT: zext.w a0, a038; RV64IMZB-NEXT: lui a1, 83886139; RV64IMZB-NEXT: addi a1, a1, -81940; RV64IMZB-NEXT: zext.w a1, a141; RV64IMZB-NEXT: mul a0, a0, a142; RV64IMZB-NEXT: srli a0, a0, 3443; RV64IMZB-NEXT: ret44 %1 = udiv i32 %a, 545 ret i32 %146}47 48; This constant requires a sub, shrli, add sequence after the mul.49define i32 @udiv_constant_add(i32 %a) nounwind {50; RV32-LABEL: udiv_constant_add:51; RV32: # %bb.0:52; RV32-NEXT: lui a1, 14979753; RV32-NEXT: addi a1, a1, -175554; RV32-NEXT: mulhu a1, a0, a155; RV32-NEXT: sub a0, a0, a156; RV32-NEXT: srli a0, a0, 157; RV32-NEXT: add a0, a0, a158; RV32-NEXT: srli a0, a0, 259; RV32-NEXT: ret60;61; RV64IM-LABEL: udiv_constant_add:62; RV64IM: # %bb.0:63; RV64IM-NEXT: lui a1, 14979764; RV64IM-NEXT: slli a2, a0, 3265; RV64IM-NEXT: addi a1, a1, -175566; RV64IM-NEXT: srli a2, a2, 3267; RV64IM-NEXT: mul a1, a2, a168; RV64IM-NEXT: srli a1, a1, 3269; RV64IM-NEXT: sub a0, a0, a170; RV64IM-NEXT: srliw a0, a0, 171; RV64IM-NEXT: add a0, a0, a172; RV64IM-NEXT: srliw a0, a0, 273; RV64IM-NEXT: ret74;75; RV64IMZB-LABEL: udiv_constant_add:76; RV64IMZB: # %bb.0:77; RV64IMZB-NEXT: lui a1, 14979778; RV64IMZB-NEXT: addi a1, a1, -175579; RV64IMZB-NEXT: zext.w a2, a080; RV64IMZB-NEXT: mul a1, a2, a181; RV64IMZB-NEXT: srli a1, a1, 3282; RV64IMZB-NEXT: sub a0, a0, a183; RV64IMZB-NEXT: srliw a0, a0, 184; RV64IMZB-NEXT: add a0, a0, a185; RV64IMZB-NEXT: srliw a0, a0, 286; RV64IMZB-NEXT: ret87 %1 = udiv i32 %a, 788 ret i32 %189}90 91define i64 @udiv64_constant_no_add(i64 %a) nounwind {92; RV32-LABEL: udiv64_constant_no_add:93; RV32: # %bb.0:94; RV32-NEXT: lui a2, 83886195; RV32-NEXT: addi a4, a2, -81996; RV32-NEXT: addi a2, a2, -82097; RV32-NEXT: mul a5, a1, a498; RV32-NEXT: mul a6, a0, a299; RV32-NEXT: mulhu a7, a0, a4100; RV32-NEXT: mul t1, a1, a2101; RV32-NEXT: mulhu t2, a1, a4102; RV32-NEXT: mulhu a0, a0, a2103; RV32-NEXT: mulhu a1, a1, a2104; RV32-NEXT: add a5, a5, a6105; RV32-NEXT: mv t0, t1106; RV32-NEXT: mv a1, a1107; RV32-NEXT: sltu a4, a5, a6108; RV32-NEXT: add a5, a5, a7109; RV32-NEXT: sltu a6, t1, t1110; RV32-NEXT: sltiu t1, t1, 0111; RV32-NEXT: add t0, t0, t2112; RV32-NEXT: mv a1, a1113; RV32-NEXT: sltu a2, a5, a7114; RV32-NEXT: add a6, a6, t1115; RV32-NEXT: sltu a5, t0, t2116; RV32-NEXT: add t0, t0, a0117; RV32-NEXT: mv a1, a1118; RV32-NEXT: add a2, a4, a2119; RV32-NEXT: add a5, a6, a5120; RV32-NEXT: sltu a0, t0, a0121; RV32-NEXT: add a0, a5, a0122; RV32-NEXT: add t0, t0, a2123; RV32-NEXT: sltu a2, t0, a2124; RV32-NEXT: srli a3, t0, 2125; RV32-NEXT: add a0, a0, a2126; RV32-NEXT: add a1, a1, a0127; RV32-NEXT: slli a0, a1, 30128; RV32-NEXT: or a0, a3, a0129; RV32-NEXT: srli a1, a1, 2130; RV32-NEXT: ret131;132; RV64-LABEL: udiv64_constant_no_add:133; RV64: # %bb.0:134; RV64-NEXT: lui a1, 1035469135; RV64-NEXT: addi a1, a1, -819136; RV64-NEXT: slli a1, a1, 12137; RV64-NEXT: addi a1, a1, -819138; RV64-NEXT: slli a1, a1, 12139; RV64-NEXT: addi a1, a1, -819140; RV64-NEXT: slli a1, a1, 12141; RV64-NEXT: addi a1, a1, -819142; RV64-NEXT: mulhu a0, a0, a1143; RV64-NEXT: srli a0, a0, 2144; RV64-NEXT: ret145 %1 = udiv i64 %a, 5146 ret i64 %1147}148 149define i64 @udiv64_constant_add(i64 %a) nounwind {150; RV32-LABEL: udiv64_constant_add:151; RV32: # %bb.0:152; RV32-NEXT: lui a2, 599186153; RV32-NEXT: lui a3, 149797154; RV32-NEXT: addi a2, a2, 1171155; RV32-NEXT: addi a3, a3, -1756156; RV32-NEXT: mul a5, a1, a2157; RV32-NEXT: mul a6, a0, a3158; RV32-NEXT: mulhu a7, a0, a2159; RV32-NEXT: mulhu t2, a1, a3160; RV32-NEXT: mv t1, t2161; RV32-NEXT: mv t1, t1162; RV32-NEXT: mul t2, a1, a3163; RV32-NEXT: mulhu a2, a1, a2164; RV32-NEXT: mulhu a3, a0, a3165; RV32-NEXT: add a5, a5, a6166; RV32-NEXT: mv t0, t2167; RV32-NEXT: sltu a6, a5, a6168; RV32-NEXT: add a5, a5, a7169; RV32-NEXT: sltu t2, t2, t2170; RV32-NEXT: sltu a5, a5, a7171; RV32-NEXT: sltiu a7, t0, 0172; RV32-NEXT: add t0, t0, a2173; RV32-NEXT: add a7, t2, a7174; RV32-NEXT: sltu a2, t0, a2175; RV32-NEXT: add t0, t0, a3176; RV32-NEXT: add a5, a6, a5177; RV32-NEXT: add a2, a7, a2178; RV32-NEXT: sltu a3, t0, a3179; RV32-NEXT: add a2, a2, a3180; RV32-NEXT: add t0, t0, a5181; RV32-NEXT: sltu a3, t0, a5182; RV32-NEXT: sub a5, a0, t0183; RV32-NEXT: sltu a0, a0, t0184; RV32-NEXT: add a2, a2, a3185; RV32-NEXT: sub a1, a1, a0186; RV32-NEXT: srli a5, a5, 1187; RV32-NEXT: add a2, t1, a2188; RV32-NEXT: sub a1, a1, a2189; RV32-NEXT: slli a0, a1, 31190; RV32-NEXT: srli a1, a1, 1191; RV32-NEXT: or a0, a5, a0192; RV32-NEXT: add a1, a1, a2193; RV32-NEXT: add a0, a0, t0194; RV32-NEXT: sltu a2, a0, t0195; RV32-NEXT: srli a0, a0, 2196; RV32-NEXT: add a1, a1, a2197; RV32-NEXT: slli a2, a1, 30198; RV32-NEXT: or a0, a0, a2199; RV32-NEXT: srli a1, a1, 2200; RV32-NEXT: ret201;202; RV64-LABEL: udiv64_constant_add:203; RV64: # %bb.0:204; RV64-NEXT: lui a1, %hi(.LCPI3_0)205; RV64-NEXT: ld a1, %lo(.LCPI3_0)(a1)206; RV64-NEXT: mulhu a1, a0, a1207; RV64-NEXT: sub a0, a0, a1208; RV64-NEXT: srli a0, a0, 1209; RV64-NEXT: add a0, a0, a1210; RV64-NEXT: srli a0, a0, 2211; RV64-NEXT: ret212 %1 = udiv i64 %a, 7213 ret i64 %1214}215 216define i8 @udiv8_constant_no_add(i8 %a) nounwind {217; RV32-LABEL: udiv8_constant_no_add:218; RV32: # %bb.0:219; RV32-NEXT: zext.b a0, a0220; RV32-NEXT: li a1, 205221; RV32-NEXT: mul a0, a0, a1222; RV32-NEXT: srli a0, a0, 10223; RV32-NEXT: ret224;225; RV64-LABEL: udiv8_constant_no_add:226; RV64: # %bb.0:227; RV64-NEXT: zext.b a0, a0228; RV64-NEXT: li a1, 205229; RV64-NEXT: mul a0, a0, a1230; RV64-NEXT: srli a0, a0, 10231; RV64-NEXT: ret232 %1 = udiv i8 %a, 5233 ret i8 %1234}235 236define i8 @udiv8_constant_add(i8 %a) nounwind {237; RV32-LABEL: udiv8_constant_add:238; RV32: # %bb.0:239; RV32-NEXT: li a1, 37240; RV32-NEXT: zext.b a2, a0241; RV32-NEXT: mul a1, a2, a1242; RV32-NEXT: srli a1, a1, 8243; RV32-NEXT: sub a0, a0, a1244; RV32-NEXT: zext.b a0, a0245; RV32-NEXT: srli a0, a0, 1246; RV32-NEXT: add a0, a0, a1247; RV32-NEXT: srli a0, a0, 2248; RV32-NEXT: ret249;250; RV64-LABEL: udiv8_constant_add:251; RV64: # %bb.0:252; RV64-NEXT: li a1, 37253; RV64-NEXT: zext.b a2, a0254; RV64-NEXT: mul a1, a2, a1255; RV64-NEXT: srli a1, a1, 8256; RV64-NEXT: sub a0, a0, a1257; RV64-NEXT: zext.b a0, a0258; RV64-NEXT: srli a0, a0, 1259; RV64-NEXT: add a0, a0, a1260; RV64-NEXT: srli a0, a0, 2261; RV64-NEXT: ret262 %1 = udiv i8 %a, 7263 ret i8 %1264}265 266define i16 @udiv16_constant_no_add(i16 %a) nounwind {267; RV32IM-LABEL: udiv16_constant_no_add:268; RV32IM: # %bb.0:269; RV32IM-NEXT: slli a0, a0, 16270; RV32IM-NEXT: lui a1, 13271; RV32IM-NEXT: srli a0, a0, 16272; RV32IM-NEXT: addi a1, a1, -819273; RV32IM-NEXT: mul a0, a0, a1274; RV32IM-NEXT: srli a0, a0, 18275; RV32IM-NEXT: ret276;277; RV32IMZB-LABEL: udiv16_constant_no_add:278; RV32IMZB: # %bb.0:279; RV32IMZB-NEXT: zext.h a0, a0280; RV32IMZB-NEXT: lui a1, 13281; RV32IMZB-NEXT: addi a1, a1, -819282; RV32IMZB-NEXT: mul a0, a0, a1283; RV32IMZB-NEXT: srli a0, a0, 18284; RV32IMZB-NEXT: ret285;286; RV64IM-LABEL: udiv16_constant_no_add:287; RV64IM: # %bb.0:288; RV64IM-NEXT: slli a0, a0, 48289; RV64IM-NEXT: lui a1, 13290; RV64IM-NEXT: srli a0, a0, 48291; RV64IM-NEXT: addi a1, a1, -819292; RV64IM-NEXT: mul a0, a0, a1293; RV64IM-NEXT: srli a0, a0, 18294; RV64IM-NEXT: ret295;296; RV64IMZB-LABEL: udiv16_constant_no_add:297; RV64IMZB: # %bb.0:298; RV64IMZB-NEXT: zext.h a0, a0299; RV64IMZB-NEXT: lui a1, 13300; RV64IMZB-NEXT: addi a1, a1, -819301; RV64IMZB-NEXT: mul a0, a0, a1302; RV64IMZB-NEXT: srli a0, a0, 18303; RV64IMZB-NEXT: ret304 %1 = udiv i16 %a, 5305 ret i16 %1306}307 308define i16 @udiv16_constant_add(i16 %a) nounwind {309; RV32IM-LABEL: udiv16_constant_add:310; RV32IM: # %bb.0:311; RV32IM-NEXT: lui a1, 2312; RV32IM-NEXT: lui a2, 16313; RV32IM-NEXT: addi a1, a1, 1171314; RV32IM-NEXT: addi a2, a2, -1315; RV32IM-NEXT: and a3, a0, a2316; RV32IM-NEXT: mul a1, a3, a1317; RV32IM-NEXT: srli a1, a1, 16318; RV32IM-NEXT: sub a0, a0, a1319; RV32IM-NEXT: and a0, a0, a2320; RV32IM-NEXT: srli a0, a0, 1321; RV32IM-NEXT: add a0, a0, a1322; RV32IM-NEXT: srli a0, a0, 2323; RV32IM-NEXT: ret324;325; RV32IMZB-LABEL: udiv16_constant_add:326; RV32IMZB: # %bb.0:327; RV32IMZB-NEXT: lui a1, 2328; RV32IMZB-NEXT: addi a1, a1, 1171329; RV32IMZB-NEXT: zext.h a2, a0330; RV32IMZB-NEXT: mul a1, a2, a1331; RV32IMZB-NEXT: srli a1, a1, 16332; RV32IMZB-NEXT: sub a0, a0, a1333; RV32IMZB-NEXT: zext.h a0, a0334; RV32IMZB-NEXT: srli a0, a0, 1335; RV32IMZB-NEXT: add a0, a0, a1336; RV32IMZB-NEXT: srli a0, a0, 2337; RV32IMZB-NEXT: ret338;339; RV64IM-LABEL: udiv16_constant_add:340; RV64IM: # %bb.0:341; RV64IM-NEXT: lui a1, 2342; RV64IM-NEXT: lui a2, 16343; RV64IM-NEXT: addi a1, a1, 1171344; RV64IM-NEXT: addi a2, a2, -1345; RV64IM-NEXT: and a3, a0, a2346; RV64IM-NEXT: mul a1, a3, a1347; RV64IM-NEXT: srli a1, a1, 16348; RV64IM-NEXT: sub a0, a0, a1349; RV64IM-NEXT: and a0, a0, a2350; RV64IM-NEXT: srli a0, a0, 1351; RV64IM-NEXT: add a0, a0, a1352; RV64IM-NEXT: srli a0, a0, 2353; RV64IM-NEXT: ret354;355; RV64IMZB-LABEL: udiv16_constant_add:356; RV64IMZB: # %bb.0:357; RV64IMZB-NEXT: lui a1, 2358; RV64IMZB-NEXT: addi a1, a1, 1171359; RV64IMZB-NEXT: zext.h a2, a0360; RV64IMZB-NEXT: mul a1, a2, a1361; RV64IMZB-NEXT: srli a1, a1, 16362; RV64IMZB-NEXT: sub a0, a0, a1363; RV64IMZB-NEXT: zext.h a0, a0364; RV64IMZB-NEXT: srli a0, a0, 1365; RV64IMZB-NEXT: add a0, a0, a1366; RV64IMZB-NEXT: srli a0, a0, 2367; RV64IMZB-NEXT: ret368 %1 = udiv i16 %a, 7369 ret i16 %1370}371 372; Test the simplest case a srli and an add after the mul. No srai.373define i32 @sdiv_constant_no_srai(i32 %a) nounwind {374; RV32-LABEL: sdiv_constant_no_srai:375; RV32: # %bb.0:376; RV32-NEXT: lui a1, 349525377; RV32-NEXT: addi a1, a1, 1366378; RV32-NEXT: mulh a0, a0, a1379; RV32-NEXT: srli a1, a0, 31380; RV32-NEXT: add a0, a0, a1381; RV32-NEXT: ret382;383; RV64-LABEL: sdiv_constant_no_srai:384; RV64: # %bb.0:385; RV64-NEXT: lui a1, 349525386; RV64-NEXT: addi a1, a1, 1366387; RV64-NEXT: sext.w a0, a0388; RV64-NEXT: mul a0, a0, a1389; RV64-NEXT: srai a0, a0, 32390; RV64-NEXT: srliw a1, a0, 31391; RV64-NEXT: addw a0, a0, a1392; RV64-NEXT: ret393 %1 = sdiv i32 %a, 3394 ret i32 %1395}396 397; This constant requires an srai between the mul and the add.398define i32 @sdiv_constant_srai(i32 %a) nounwind {399; RV32-LABEL: sdiv_constant_srai:400; RV32: # %bb.0:401; RV32-NEXT: lui a1, 419430402; RV32-NEXT: addi a1, a1, 1639403; RV32-NEXT: mulh a0, a0, a1404; RV32-NEXT: srai a0, a0, 1405; RV32-NEXT: srli a1, a0, 31406; RV32-NEXT: add a0, a0, a1407; RV32-NEXT: ret408;409; RV64-LABEL: sdiv_constant_srai:410; RV64: # %bb.0:411; RV64-NEXT: lui a1, 419430412; RV64-NEXT: addi a1, a1, 1639413; RV64-NEXT: sext.w a0, a0414; RV64-NEXT: mul a0, a0, a1415; RV64-NEXT: srai a0, a0, 33416; RV64-NEXT: srliw a1, a0, 31417; RV64-NEXT: addw a0, a0, a1418; RV64-NEXT: ret419 %1 = sdiv i32 %a, 5420 ret i32 %1421}422 423; This constant requires an add and an srai after the mul.424define i32 @sdiv_constant_add_srai(i32 %a) nounwind {425; RV32-LABEL: sdiv_constant_add_srai:426; RV32: # %bb.0:427; RV32-NEXT: lui a1, 599186428; RV32-NEXT: addi a1, a1, 1171429; RV32-NEXT: mulh a1, a0, a1430; RV32-NEXT: add a0, a1, a0431; RV32-NEXT: srai a0, a0, 2432; RV32-NEXT: srli a1, a0, 31433; RV32-NEXT: add a0, a0, a1434; RV32-NEXT: ret435;436; RV64-LABEL: sdiv_constant_add_srai:437; RV64: # %bb.0:438; RV64-NEXT: lui a1, 599186439; RV64-NEXT: addi a1, a1, 1171440; RV64-NEXT: sext.w a2, a0441; RV64-NEXT: mul a1, a2, a1442; RV64-NEXT: srai a1, a1, 32443; RV64-NEXT: add a0, a1, a0444; RV64-NEXT: sraiw a0, a0, 2445; RV64-NEXT: srliw a1, a0, 31446; RV64-NEXT: addw a0, a0, a1447; RV64-NEXT: ret448 %1 = sdiv i32 %a, 7449 ret i32 %1450}451 452; This constant requires a sub and an srai after the mul.453define i32 @sdiv_constant_sub_srai(i32 %a) nounwind {454; RV32-LABEL: sdiv_constant_sub_srai:455; RV32: # %bb.0:456; RV32-NEXT: lui a1, 449390457; RV32-NEXT: addi a1, a1, -1171458; RV32-NEXT: mulh a1, a0, a1459; RV32-NEXT: sub a1, a1, a0460; RV32-NEXT: srai a0, a1, 2461; RV32-NEXT: srli a1, a0, 31462; RV32-NEXT: add a0, a0, a1463; RV32-NEXT: ret464;465; RV64-LABEL: sdiv_constant_sub_srai:466; RV64: # %bb.0:467; RV64-NEXT: lui a1, 449390468; RV64-NEXT: addi a1, a1, -1171469; RV64-NEXT: sext.w a2, a0470; RV64-NEXT: mul a1, a2, a1471; RV64-NEXT: srai a1, a1, 32472; RV64-NEXT: sub a1, a1, a0473; RV64-NEXT: sraiw a0, a1, 2474; RV64-NEXT: srliw a1, a0, 31475; RV64-NEXT: addw a0, a0, a1476; RV64-NEXT: ret477 %1 = sdiv i32 %a, -7478 ret i32 %1479}480 481define i64 @sdiv64_constant_no_srai(i64 %a) nounwind {482; RV32-LABEL: sdiv64_constant_no_srai:483; RV32: # %bb.0:484; RV32-NEXT: addi sp, sp, -16485; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill486; RV32-NEXT: li a2, 3487; RV32-NEXT: li a3, 0488; RV32-NEXT: call __divdi3489; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload490; RV32-NEXT: addi sp, sp, 16491; RV32-NEXT: ret492;493; RV64-LABEL: sdiv64_constant_no_srai:494; RV64: # %bb.0:495; RV64-NEXT: lui a1, %hi(.LCPI12_0)496; RV64-NEXT: ld a1, %lo(.LCPI12_0)(a1)497; RV64-NEXT: mulh a0, a0, a1498; RV64-NEXT: srli a1, a0, 63499; RV64-NEXT: add a0, a0, a1500; RV64-NEXT: ret501 %1 = sdiv i64 %a, 3502 ret i64 %1503}504 505define i64 @sdiv64_constant_srai(i64 %a) nounwind {506; RV32-LABEL: sdiv64_constant_srai:507; RV32: # %bb.0:508; RV32-NEXT: addi sp, sp, -16509; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill510; RV32-NEXT: li a2, 5511; RV32-NEXT: li a3, 0512; RV32-NEXT: call __divdi3513; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload514; RV32-NEXT: addi sp, sp, 16515; RV32-NEXT: ret516;517; RV64-LABEL: sdiv64_constant_srai:518; RV64: # %bb.0:519; RV64-NEXT: lui a1, %hi(.LCPI13_0)520; RV64-NEXT: ld a1, %lo(.LCPI13_0)(a1)521; RV64-NEXT: mulh a0, a0, a1522; RV64-NEXT: srai a0, a0, 1523; RV64-NEXT: srli a1, a0, 63524; RV64-NEXT: add a0, a0, a1525; RV64-NEXT: ret526 %1 = sdiv i64 %a, 5527 ret i64 %1528}529 530define i64 @sdiv64_constant_add_srai(i64 %a) nounwind {531; RV32-LABEL: sdiv64_constant_add_srai:532; RV32: # %bb.0:533; RV32-NEXT: addi sp, sp, -16534; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill535; RV32-NEXT: li a2, 15536; RV32-NEXT: li a3, 0537; RV32-NEXT: call __divdi3538; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload539; RV32-NEXT: addi sp, sp, 16540; RV32-NEXT: ret541;542; RV64-LABEL: sdiv64_constant_add_srai:543; RV64: # %bb.0:544; RV64-NEXT: lui a1, 1017993545; RV64-NEXT: addi a1, a1, -1911546; RV64-NEXT: slli a1, a1, 12547; RV64-NEXT: addi a1, a1, -1911548; RV64-NEXT: slli a1, a1, 12549; RV64-NEXT: addi a1, a1, -1911550; RV64-NEXT: slli a1, a1, 12551; RV64-NEXT: addi a1, a1, -1911552; RV64-NEXT: mulh a1, a0, a1553; RV64-NEXT: add a0, a1, a0554; RV64-NEXT: srai a0, a0, 3555; RV64-NEXT: srli a1, a0, 63556; RV64-NEXT: add a0, a0, a1557; RV64-NEXT: ret558 %1 = sdiv i64 %a, 15559 ret i64 %1560}561 562define i64 @sdiv64_constant_sub_srai(i64 %a) nounwind {563; RV32-LABEL: sdiv64_constant_sub_srai:564; RV32: # %bb.0:565; RV32-NEXT: addi sp, sp, -16566; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill567; RV32-NEXT: li a2, -3568; RV32-NEXT: li a3, -1569; RV32-NEXT: call __divdi3570; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload571; RV32-NEXT: addi sp, sp, 16572; RV32-NEXT: ret573;574; RV64-LABEL: sdiv64_constant_sub_srai:575; RV64: # %bb.0:576; RV64-NEXT: lui a1, 21845577; RV64-NEXT: addi a1, a1, 1365578; RV64-NEXT: slli a1, a1, 12579; RV64-NEXT: addi a1, a1, 1365580; RV64-NEXT: slli a1, a1, 12581; RV64-NEXT: addi a1, a1, 1365582; RV64-NEXT: slli a1, a1, 12583; RV64-NEXT: addi a1, a1, 1365584; RV64-NEXT: mulh a1, a0, a1585; RV64-NEXT: sub a1, a1, a0586; RV64-NEXT: srai a0, a1, 1587; RV64-NEXT: srli a1, a0, 63588; RV64-NEXT: add a0, a0, a1589; RV64-NEXT: ret590 %1 = sdiv i64 %a, -3591 ret i64 %1592}593 594define i8 @sdiv8_constant_no_srai(i8 %a) nounwind {595; RV32IM-LABEL: sdiv8_constant_no_srai:596; RV32IM: # %bb.0:597; RV32IM-NEXT: li a1, 86598; RV32IM-NEXT: slli a0, a0, 24599; RV32IM-NEXT: srai a0, a0, 24600; RV32IM-NEXT: mul a0, a0, a1601; RV32IM-NEXT: slli a0, a0, 16602; RV32IM-NEXT: srai a0, a0, 24603; RV32IM-NEXT: zext.b a1, a0604; RV32IM-NEXT: srli a1, a1, 7605; RV32IM-NEXT: add a0, a0, a1606; RV32IM-NEXT: ret607;608; RV32IMZB-LABEL: sdiv8_constant_no_srai:609; RV32IMZB: # %bb.0:610; RV32IMZB-NEXT: li a1, 86611; RV32IMZB-NEXT: sext.b a0, a0612; RV32IMZB-NEXT: mul a0, a0, a1613; RV32IMZB-NEXT: sext.h a0, a0614; RV32IMZB-NEXT: srai a0, a0, 8615; RV32IMZB-NEXT: zext.b a1, a0616; RV32IMZB-NEXT: srli a1, a1, 7617; RV32IMZB-NEXT: add a0, a0, a1618; RV32IMZB-NEXT: ret619;620; RV64IM-LABEL: sdiv8_constant_no_srai:621; RV64IM: # %bb.0:622; RV64IM-NEXT: li a1, 86623; RV64IM-NEXT: slli a0, a0, 56624; RV64IM-NEXT: srai a0, a0, 56625; RV64IM-NEXT: mul a0, a0, a1626; RV64IM-NEXT: slli a0, a0, 48627; RV64IM-NEXT: srai a0, a0, 56628; RV64IM-NEXT: zext.b a1, a0629; RV64IM-NEXT: srli a1, a1, 7630; RV64IM-NEXT: add a0, a0, a1631; RV64IM-NEXT: ret632;633; RV64IMZB-LABEL: sdiv8_constant_no_srai:634; RV64IMZB: # %bb.0:635; RV64IMZB-NEXT: li a1, 86636; RV64IMZB-NEXT: sext.b a0, a0637; RV64IMZB-NEXT: mul a0, a0, a1638; RV64IMZB-NEXT: sext.h a0, a0639; RV64IMZB-NEXT: srai a0, a0, 8640; RV64IMZB-NEXT: zext.b a1, a0641; RV64IMZB-NEXT: srli a1, a1, 7642; RV64IMZB-NEXT: add a0, a0, a1643; RV64IMZB-NEXT: ret644 %1 = sdiv i8 %a, 3645 ret i8 %1646}647 648define i8 @sdiv8_constant_srai(i8 %a) nounwind {649; RV32IM-LABEL: sdiv8_constant_srai:650; RV32IM: # %bb.0:651; RV32IM-NEXT: li a1, 103652; RV32IM-NEXT: slli a0, a0, 24653; RV32IM-NEXT: srai a0, a0, 24654; RV32IM-NEXT: mul a0, a0, a1655; RV32IM-NEXT: slli a0, a0, 16656; RV32IM-NEXT: srai a0, a0, 25657; RV32IM-NEXT: zext.b a1, a0658; RV32IM-NEXT: srli a1, a1, 7659; RV32IM-NEXT: add a0, a0, a1660; RV32IM-NEXT: ret661;662; RV32IMZB-LABEL: sdiv8_constant_srai:663; RV32IMZB: # %bb.0:664; RV32IMZB-NEXT: li a1, 103665; RV32IMZB-NEXT: sext.b a0, a0666; RV32IMZB-NEXT: mul a0, a0, a1667; RV32IMZB-NEXT: sext.h a0, a0668; RV32IMZB-NEXT: srai a0, a0, 9669; RV32IMZB-NEXT: zext.b a1, a0670; RV32IMZB-NEXT: srli a1, a1, 7671; RV32IMZB-NEXT: add a0, a0, a1672; RV32IMZB-NEXT: ret673;674; RV64IM-LABEL: sdiv8_constant_srai:675; RV64IM: # %bb.0:676; RV64IM-NEXT: li a1, 103677; RV64IM-NEXT: slli a0, a0, 56678; RV64IM-NEXT: srai a0, a0, 56679; RV64IM-NEXT: mul a0, a0, a1680; RV64IM-NEXT: slli a0, a0, 48681; RV64IM-NEXT: srai a0, a0, 57682; RV64IM-NEXT: zext.b a1, a0683; RV64IM-NEXT: srli a1, a1, 7684; RV64IM-NEXT: add a0, a0, a1685; RV64IM-NEXT: ret686;687; RV64IMZB-LABEL: sdiv8_constant_srai:688; RV64IMZB: # %bb.0:689; RV64IMZB-NEXT: li a1, 103690; RV64IMZB-NEXT: sext.b a0, a0691; RV64IMZB-NEXT: mul a0, a0, a1692; RV64IMZB-NEXT: sext.h a0, a0693; RV64IMZB-NEXT: srai a0, a0, 9694; RV64IMZB-NEXT: zext.b a1, a0695; RV64IMZB-NEXT: srli a1, a1, 7696; RV64IMZB-NEXT: add a0, a0, a1697; RV64IMZB-NEXT: ret698 %1 = sdiv i8 %a, 5699 ret i8 %1700}701 702define i8 @sdiv8_constant_add_srai(i8 %a) nounwind {703; RV32IM-LABEL: sdiv8_constant_add_srai:704; RV32IM: # %bb.0:705; RV32IM-NEXT: li a1, -109706; RV32IM-NEXT: slli a2, a0, 24707; RV32IM-NEXT: srai a2, a2, 24708; RV32IM-NEXT: mul a1, a2, a1709; RV32IM-NEXT: slli a1, a1, 16710; RV32IM-NEXT: srai a1, a1, 24711; RV32IM-NEXT: add a0, a1, a0712; RV32IM-NEXT: slli a0, a0, 24713; RV32IM-NEXT: srai a0, a0, 26714; RV32IM-NEXT: zext.b a1, a0715; RV32IM-NEXT: srli a1, a1, 7716; RV32IM-NEXT: add a0, a0, a1717; RV32IM-NEXT: ret718;719; RV32IMZB-LABEL: sdiv8_constant_add_srai:720; RV32IMZB: # %bb.0:721; RV32IMZB-NEXT: li a1, -109722; RV32IMZB-NEXT: sext.b a2, a0723; RV32IMZB-NEXT: mul a1, a2, a1724; RV32IMZB-NEXT: sext.h a1, a1725; RV32IMZB-NEXT: srai a1, a1, 8726; RV32IMZB-NEXT: add a0, a1, a0727; RV32IMZB-NEXT: sext.b a0, a0728; RV32IMZB-NEXT: srai a0, a0, 2729; RV32IMZB-NEXT: zext.b a1, a0730; RV32IMZB-NEXT: srli a1, a1, 7731; RV32IMZB-NEXT: add a0, a0, a1732; RV32IMZB-NEXT: ret733;734; RV64IM-LABEL: sdiv8_constant_add_srai:735; RV64IM: # %bb.0:736; RV64IM-NEXT: li a1, -109737; RV64IM-NEXT: slli a2, a0, 56738; RV64IM-NEXT: srai a2, a2, 56739; RV64IM-NEXT: mul a1, a2, a1740; RV64IM-NEXT: slli a1, a1, 48741; RV64IM-NEXT: srai a1, a1, 56742; RV64IM-NEXT: add a0, a1, a0743; RV64IM-NEXT: slli a0, a0, 56744; RV64IM-NEXT: srai a0, a0, 58745; RV64IM-NEXT: zext.b a1, a0746; RV64IM-NEXT: srli a1, a1, 7747; RV64IM-NEXT: add a0, a0, a1748; RV64IM-NEXT: ret749;750; RV64IMZB-LABEL: sdiv8_constant_add_srai:751; RV64IMZB: # %bb.0:752; RV64IMZB-NEXT: li a1, -109753; RV64IMZB-NEXT: sext.b a2, a0754; RV64IMZB-NEXT: mul a1, a2, a1755; RV64IMZB-NEXT: sext.h a1, a1756; RV64IMZB-NEXT: srai a1, a1, 8757; RV64IMZB-NEXT: add a0, a1, a0758; RV64IMZB-NEXT: sext.b a0, a0759; RV64IMZB-NEXT: srai a0, a0, 2760; RV64IMZB-NEXT: zext.b a1, a0761; RV64IMZB-NEXT: srli a1, a1, 7762; RV64IMZB-NEXT: add a0, a0, a1763; RV64IMZB-NEXT: ret764 %1 = sdiv i8 %a, 7765 ret i8 %1766}767 768define i8 @sdiv8_constant_sub_srai(i8 %a) nounwind {769; RV32IM-LABEL: sdiv8_constant_sub_srai:770; RV32IM: # %bb.0:771; RV32IM-NEXT: li a1, 109772; RV32IM-NEXT: slli a2, a0, 24773; RV32IM-NEXT: srai a2, a2, 24774; RV32IM-NEXT: mul a1, a2, a1775; RV32IM-NEXT: slli a1, a1, 16776; RV32IM-NEXT: srai a1, a1, 24777; RV32IM-NEXT: sub a1, a1, a0778; RV32IM-NEXT: slli a1, a1, 24779; RV32IM-NEXT: srai a0, a1, 26780; RV32IM-NEXT: zext.b a1, a0781; RV32IM-NEXT: srli a1, a1, 7782; RV32IM-NEXT: add a0, a0, a1783; RV32IM-NEXT: ret784;785; RV32IMZB-LABEL: sdiv8_constant_sub_srai:786; RV32IMZB: # %bb.0:787; RV32IMZB-NEXT: li a1, 109788; RV32IMZB-NEXT: sext.b a2, a0789; RV32IMZB-NEXT: mul a1, a2, a1790; RV32IMZB-NEXT: sext.h a1, a1791; RV32IMZB-NEXT: srai a1, a1, 8792; RV32IMZB-NEXT: sub a1, a1, a0793; RV32IMZB-NEXT: sext.b a0, a1794; RV32IMZB-NEXT: srai a0, a0, 2795; RV32IMZB-NEXT: zext.b a1, a0796; RV32IMZB-NEXT: srli a1, a1, 7797; RV32IMZB-NEXT: add a0, a0, a1798; RV32IMZB-NEXT: ret799;800; RV64IM-LABEL: sdiv8_constant_sub_srai:801; RV64IM: # %bb.0:802; RV64IM-NEXT: li a1, 109803; RV64IM-NEXT: slli a2, a0, 56804; RV64IM-NEXT: srai a2, a2, 56805; RV64IM-NEXT: mul a1, a2, a1806; RV64IM-NEXT: slli a1, a1, 48807; RV64IM-NEXT: srai a1, a1, 56808; RV64IM-NEXT: sub a1, a1, a0809; RV64IM-NEXT: slli a1, a1, 56810; RV64IM-NEXT: srai a0, a1, 58811; RV64IM-NEXT: zext.b a1, a0812; RV64IM-NEXT: srli a1, a1, 7813; RV64IM-NEXT: add a0, a0, a1814; RV64IM-NEXT: ret815;816; RV64IMZB-LABEL: sdiv8_constant_sub_srai:817; RV64IMZB: # %bb.0:818; RV64IMZB-NEXT: li a1, 109819; RV64IMZB-NEXT: sext.b a2, a0820; RV64IMZB-NEXT: mul a1, a2, a1821; RV64IMZB-NEXT: sext.h a1, a1822; RV64IMZB-NEXT: srai a1, a1, 8823; RV64IMZB-NEXT: sub a1, a1, a0824; RV64IMZB-NEXT: sext.b a0, a1825; RV64IMZB-NEXT: srai a0, a0, 2826; RV64IMZB-NEXT: zext.b a1, a0827; RV64IMZB-NEXT: srli a1, a1, 7828; RV64IMZB-NEXT: add a0, a0, a1829; RV64IMZB-NEXT: ret830 %1 = sdiv i8 %a, -7831 ret i8 %1832}833 834define i16 @sdiv16_constant_no_srai(i16 %a) nounwind {835; RV32IM-LABEL: sdiv16_constant_no_srai:836; RV32IM: # %bb.0:837; RV32IM-NEXT: lui a1, 5838; RV32IM-NEXT: slli a0, a0, 16839; RV32IM-NEXT: addi a1, a1, 1366840; RV32IM-NEXT: srai a0, a0, 16841; RV32IM-NEXT: mul a0, a0, a1842; RV32IM-NEXT: srai a0, a0, 16843; RV32IM-NEXT: slli a1, a0, 16844; RV32IM-NEXT: srli a1, a1, 16845; RV32IM-NEXT: srli a1, a1, 15846; RV32IM-NEXT: add a0, a0, a1847; RV32IM-NEXT: ret848;849; RV32IMZB-LABEL: sdiv16_constant_no_srai:850; RV32IMZB: # %bb.0:851; RV32IMZB-NEXT: lui a1, 5852; RV32IMZB-NEXT: addi a1, a1, 1366853; RV32IMZB-NEXT: sext.h a0, a0854; RV32IMZB-NEXT: mul a0, a0, a1855; RV32IMZB-NEXT: srai a0, a0, 16856; RV32IMZB-NEXT: zext.h a1, a0857; RV32IMZB-NEXT: srli a1, a1, 15858; RV32IMZB-NEXT: add a0, a0, a1859; RV32IMZB-NEXT: ret860;861; RV64IM-LABEL: sdiv16_constant_no_srai:862; RV64IM: # %bb.0:863; RV64IM-NEXT: lui a1, 5864; RV64IM-NEXT: slli a0, a0, 48865; RV64IM-NEXT: addi a1, a1, 1366866; RV64IM-NEXT: srai a0, a0, 48867; RV64IM-NEXT: mul a0, a0, a1868; RV64IM-NEXT: sraiw a0, a0, 16869; RV64IM-NEXT: slli a1, a0, 48870; RV64IM-NEXT: srli a1, a1, 48871; RV64IM-NEXT: srli a1, a1, 15872; RV64IM-NEXT: add a0, a0, a1873; RV64IM-NEXT: ret874;875; RV64IMZB-LABEL: sdiv16_constant_no_srai:876; RV64IMZB: # %bb.0:877; RV64IMZB-NEXT: lui a1, 5878; RV64IMZB-NEXT: addi a1, a1, 1366879; RV64IMZB-NEXT: sext.h a0, a0880; RV64IMZB-NEXT: mul a0, a0, a1881; RV64IMZB-NEXT: sraiw a0, a0, 16882; RV64IMZB-NEXT: zext.h a1, a0883; RV64IMZB-NEXT: srli a1, a1, 15884; RV64IMZB-NEXT: add a0, a0, a1885; RV64IMZB-NEXT: ret886 %1 = sdiv i16 %a, 3887 ret i16 %1888}889 890define i16 @sdiv16_constant_srai(i16 %a) nounwind {891; RV32IM-LABEL: sdiv16_constant_srai:892; RV32IM: # %bb.0:893; RV32IM-NEXT: lui a1, 6894; RV32IM-NEXT: slli a0, a0, 16895; RV32IM-NEXT: addi a1, a1, 1639896; RV32IM-NEXT: srai a0, a0, 16897; RV32IM-NEXT: mul a0, a0, a1898; RV32IM-NEXT: srai a0, a0, 17899; RV32IM-NEXT: slli a1, a0, 16900; RV32IM-NEXT: srli a1, a1, 16901; RV32IM-NEXT: srli a1, a1, 15902; RV32IM-NEXT: add a0, a0, a1903; RV32IM-NEXT: ret904;905; RV32IMZB-LABEL: sdiv16_constant_srai:906; RV32IMZB: # %bb.0:907; RV32IMZB-NEXT: lui a1, 6908; RV32IMZB-NEXT: addi a1, a1, 1639909; RV32IMZB-NEXT: sext.h a0, a0910; RV32IMZB-NEXT: mul a0, a0, a1911; RV32IMZB-NEXT: srai a0, a0, 17912; RV32IMZB-NEXT: zext.h a1, a0913; RV32IMZB-NEXT: srli a1, a1, 15914; RV32IMZB-NEXT: add a0, a0, a1915; RV32IMZB-NEXT: ret916;917; RV64IM-LABEL: sdiv16_constant_srai:918; RV64IM: # %bb.0:919; RV64IM-NEXT: lui a1, 6920; RV64IM-NEXT: slli a0, a0, 48921; RV64IM-NEXT: addi a1, a1, 1639922; RV64IM-NEXT: srai a0, a0, 48923; RV64IM-NEXT: mul a0, a0, a1924; RV64IM-NEXT: sraiw a0, a0, 17925; RV64IM-NEXT: slli a1, a0, 48926; RV64IM-NEXT: srli a1, a1, 48927; RV64IM-NEXT: srli a1, a1, 15928; RV64IM-NEXT: add a0, a0, a1929; RV64IM-NEXT: ret930;931; RV64IMZB-LABEL: sdiv16_constant_srai:932; RV64IMZB: # %bb.0:933; RV64IMZB-NEXT: lui a1, 6934; RV64IMZB-NEXT: addi a1, a1, 1639935; RV64IMZB-NEXT: sext.h a0, a0936; RV64IMZB-NEXT: mul a0, a0, a1937; RV64IMZB-NEXT: sraiw a0, a0, 17938; RV64IMZB-NEXT: zext.h a1, a0939; RV64IMZB-NEXT: srli a1, a1, 15940; RV64IMZB-NEXT: add a0, a0, a1941; RV64IMZB-NEXT: ret942 %1 = sdiv i16 %a, 5943 ret i16 %1944}945 946define i16 @sdiv16_constant_add_srai(i16 %a) nounwind {947; RV32IM-LABEL: sdiv16_constant_add_srai:948; RV32IM: # %bb.0:949; RV32IM-NEXT: lui a1, 1048569950; RV32IM-NEXT: slli a2, a0, 16951; RV32IM-NEXT: addi a1, a1, -1911952; RV32IM-NEXT: srai a2, a2, 16953; RV32IM-NEXT: mul a1, a2, a1954; RV32IM-NEXT: srai a1, a1, 16955; RV32IM-NEXT: add a0, a1, a0956; RV32IM-NEXT: slli a0, a0, 16957; RV32IM-NEXT: srai a0, a0, 19958; RV32IM-NEXT: slli a1, a0, 16959; RV32IM-NEXT: srli a1, a1, 16960; RV32IM-NEXT: srli a1, a1, 15961; RV32IM-NEXT: add a0, a0, a1962; RV32IM-NEXT: ret963;964; RV32IMZB-LABEL: sdiv16_constant_add_srai:965; RV32IMZB: # %bb.0:966; RV32IMZB-NEXT: lui a1, 1048569967; RV32IMZB-NEXT: addi a1, a1, -1911968; RV32IMZB-NEXT: sext.h a2, a0969; RV32IMZB-NEXT: mul a1, a2, a1970; RV32IMZB-NEXT: srai a1, a1, 16971; RV32IMZB-NEXT: add a0, a1, a0972; RV32IMZB-NEXT: sext.h a0, a0973; RV32IMZB-NEXT: srai a0, a0, 3974; RV32IMZB-NEXT: zext.h a1, a0975; RV32IMZB-NEXT: srli a1, a1, 15976; RV32IMZB-NEXT: add a0, a0, a1977; RV32IMZB-NEXT: ret978;979; RV64IM-LABEL: sdiv16_constant_add_srai:980; RV64IM: # %bb.0:981; RV64IM-NEXT: lui a1, 1048569982; RV64IM-NEXT: slli a2, a0, 48983; RV64IM-NEXT: addi a1, a1, -1911984; RV64IM-NEXT: srai a2, a2, 48985; RV64IM-NEXT: mul a1, a2, a1986; RV64IM-NEXT: sraiw a1, a1, 16987; RV64IM-NEXT: add a0, a1, a0988; RV64IM-NEXT: slli a0, a0, 48989; RV64IM-NEXT: srai a0, a0, 51990; RV64IM-NEXT: slli a1, a0, 48991; RV64IM-NEXT: srli a1, a1, 48992; RV64IM-NEXT: srli a1, a1, 15993; RV64IM-NEXT: add a0, a0, a1994; RV64IM-NEXT: ret995;996; RV64IMZB-LABEL: sdiv16_constant_add_srai:997; RV64IMZB: # %bb.0:998; RV64IMZB-NEXT: lui a1, 1048569999; RV64IMZB-NEXT: addi a1, a1, -19111000; RV64IMZB-NEXT: sext.h a2, a01001; RV64IMZB-NEXT: mul a1, a2, a11002; RV64IMZB-NEXT: sraiw a1, a1, 161003; RV64IMZB-NEXT: add a0, a1, a01004; RV64IMZB-NEXT: sext.h a0, a01005; RV64IMZB-NEXT: srai a0, a0, 31006; RV64IMZB-NEXT: zext.h a1, a01007; RV64IMZB-NEXT: srli a1, a1, 151008; RV64IMZB-NEXT: add a0, a0, a11009; RV64IMZB-NEXT: ret1010 %1 = sdiv i16 %a, 151011 ret i16 %11012}1013 1014define i16 @sdiv16_constant_sub_srai(i16 %a) nounwind {1015; RV32IM-LABEL: sdiv16_constant_sub_srai:1016; RV32IM: # %bb.0:1017; RV32IM-NEXT: lui a1, 71018; RV32IM-NEXT: slli a2, a0, 161019; RV32IM-NEXT: addi a1, a1, 19111020; RV32IM-NEXT: srai a2, a2, 161021; RV32IM-NEXT: mul a1, a2, a11022; RV32IM-NEXT: srai a1, a1, 161023; RV32IM-NEXT: sub a1, a1, a01024; RV32IM-NEXT: slli a1, a1, 161025; RV32IM-NEXT: srai a0, a1, 191026; RV32IM-NEXT: slli a1, a0, 161027; RV32IM-NEXT: srli a1, a1, 161028; RV32IM-NEXT: srli a1, a1, 151029; RV32IM-NEXT: add a0, a0, a11030; RV32IM-NEXT: ret1031;1032; RV32IMZB-LABEL: sdiv16_constant_sub_srai:1033; RV32IMZB: # %bb.0:1034; RV32IMZB-NEXT: lui a1, 71035; RV32IMZB-NEXT: addi a1, a1, 19111036; RV32IMZB-NEXT: sext.h a2, a01037; RV32IMZB-NEXT: mul a1, a2, a11038; RV32IMZB-NEXT: srai a1, a1, 161039; RV32IMZB-NEXT: sub a1, a1, a01040; RV32IMZB-NEXT: sext.h a0, a11041; RV32IMZB-NEXT: srai a0, a0, 31042; RV32IMZB-NEXT: zext.h a1, a01043; RV32IMZB-NEXT: srli a1, a1, 151044; RV32IMZB-NEXT: add a0, a0, a11045; RV32IMZB-NEXT: ret1046;1047; RV64IM-LABEL: sdiv16_constant_sub_srai:1048; RV64IM: # %bb.0:1049; RV64IM-NEXT: lui a1, 71050; RV64IM-NEXT: slli a2, a0, 481051; RV64IM-NEXT: addi a1, a1, 19111052; RV64IM-NEXT: srai a2, a2, 481053; RV64IM-NEXT: mul a1, a2, a11054; RV64IM-NEXT: sraiw a1, a1, 161055; RV64IM-NEXT: sub a1, a1, a01056; RV64IM-NEXT: slli a1, a1, 481057; RV64IM-NEXT: srai a0, a1, 511058; RV64IM-NEXT: slli a1, a0, 481059; RV64IM-NEXT: srli a1, a1, 481060; RV64IM-NEXT: srli a1, a1, 151061; RV64IM-NEXT: add a0, a0, a11062; RV64IM-NEXT: ret1063;1064; RV64IMZB-LABEL: sdiv16_constant_sub_srai:1065; RV64IMZB: # %bb.0:1066; RV64IMZB-NEXT: lui a1, 71067; RV64IMZB-NEXT: addi a1, a1, 19111068; RV64IMZB-NEXT: sext.h a2, a01069; RV64IMZB-NEXT: mul a1, a2, a11070; RV64IMZB-NEXT: sraiw a1, a1, 161071; RV64IMZB-NEXT: sub a1, a1, a01072; RV64IMZB-NEXT: sext.h a0, a11073; RV64IMZB-NEXT: srai a0, a0, 31074; RV64IMZB-NEXT: zext.h a1, a01075; RV64IMZB-NEXT: srli a1, a1, 151076; RV64IMZB-NEXT: add a0, a0, a11077; RV64IMZB-NEXT: ret1078 %1 = sdiv i16 %a, -151079 ret i16 %11080}1081