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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -global-isel -mattr=+f -verify-machineinstrs < %s \3; RUN: -target-abi=ilp32f | FileCheck -check-prefix=CHECKIF %s4; RUN: llc -mtriple=riscv64 -global-isel -mattr=+f -verify-machineinstrs < %s \5; RUN: -target-abi=lp64f | FileCheck -check-prefix=CHECKIF %s6; RUN: llc -mtriple=riscv32 -global-isel -verify-machineinstrs < %s \7; RUN: | FileCheck -check-prefix=RV32I %s8; RUN: llc -mtriple=riscv64 -global-isel -verify-machineinstrs < %s \9; RUN: | FileCheck -check-prefix=RV64I %s10 11; These tests are each targeted at a particular RISC-V FPU instruction.12; Compares and conversions can be found in float-fcmp.ll and float-convert.ll13; respectively. Some other float-*.ll files in this folder exercise LLVM IR14; instructions that don't directly match a RISC-V instruction.15 16define float @fadd_s(float %a, float %b) nounwind {17; CHECKIF-LABEL: fadd_s:18; CHECKIF: # %bb.0:19; CHECKIF-NEXT: fadd.s fa0, fa0, fa120; CHECKIF-NEXT: ret21;22; RV32I-LABEL: fadd_s:23; RV32I: # %bb.0:24; RV32I-NEXT: addi sp, sp, -1625; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill26; RV32I-NEXT: call __addsf327; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload28; RV32I-NEXT: addi sp, sp, 1629; RV32I-NEXT: ret30;31; RV64I-LABEL: fadd_s:32; RV64I: # %bb.0:33; RV64I-NEXT: addi sp, sp, -1634; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill35; RV64I-NEXT: call __addsf336; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload37; RV64I-NEXT: addi sp, sp, 1638; RV64I-NEXT: ret39 %1 = fadd float %a, %b40 ret float %141}42 43define float @fsub_s(float %a, float %b) nounwind {44; CHECKIF-LABEL: fsub_s:45; CHECKIF: # %bb.0:46; CHECKIF-NEXT: fsub.s fa0, fa0, fa147; CHECKIF-NEXT: ret48;49; RV32I-LABEL: fsub_s:50; RV32I: # %bb.0:51; RV32I-NEXT: addi sp, sp, -1652; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill53; RV32I-NEXT: call __subsf354; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload55; RV32I-NEXT: addi sp, sp, 1656; RV32I-NEXT: ret57;58; RV64I-LABEL: fsub_s:59; RV64I: # %bb.0:60; RV64I-NEXT: addi sp, sp, -1661; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill62; RV64I-NEXT: call __subsf363; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload64; RV64I-NEXT: addi sp, sp, 1665; RV64I-NEXT: ret66 %1 = fsub float %a, %b67 ret float %168}69 70define float @fmul_s(float %a, float %b) nounwind {71; CHECKIF-LABEL: fmul_s:72; CHECKIF: # %bb.0:73; CHECKIF-NEXT: fmul.s fa0, fa0, fa174; CHECKIF-NEXT: ret75;76; RV32I-LABEL: fmul_s:77; RV32I: # %bb.0:78; RV32I-NEXT: addi sp, sp, -1679; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill80; RV32I-NEXT: call __mulsf381; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload82; RV32I-NEXT: addi sp, sp, 1683; RV32I-NEXT: ret84;85; RV64I-LABEL: fmul_s:86; RV64I: # %bb.0:87; RV64I-NEXT: addi sp, sp, -1688; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill89; RV64I-NEXT: call __mulsf390; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload91; RV64I-NEXT: addi sp, sp, 1692; RV64I-NEXT: ret93 %1 = fmul float %a, %b94 ret float %195}96 97define float @fdiv_s(float %a, float %b) nounwind {98; CHECKIF-LABEL: fdiv_s:99; CHECKIF: # %bb.0:100; CHECKIF-NEXT: fdiv.s fa0, fa0, fa1101; CHECKIF-NEXT: ret102;103; RV32I-LABEL: fdiv_s:104; RV32I: # %bb.0:105; RV32I-NEXT: addi sp, sp, -16106; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill107; RV32I-NEXT: call __divsf3108; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload109; RV32I-NEXT: addi sp, sp, 16110; RV32I-NEXT: ret111;112; RV64I-LABEL: fdiv_s:113; RV64I: # %bb.0:114; RV64I-NEXT: addi sp, sp, -16115; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill116; RV64I-NEXT: call __divsf3117; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload118; RV64I-NEXT: addi sp, sp, 16119; RV64I-NEXT: ret120 %1 = fdiv float %a, %b121 ret float %1122}123 124define float @fsqrt_s(float %a) nounwind {125; CHECKIF-LABEL: fsqrt_s:126; CHECKIF: # %bb.0:127; CHECKIF-NEXT: fsqrt.s fa0, fa0128; CHECKIF-NEXT: ret129;130; RV32I-LABEL: fsqrt_s:131; RV32I: # %bb.0:132; RV32I-NEXT: addi sp, sp, -16133; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill134; RV32I-NEXT: call sqrtf135; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload136; RV32I-NEXT: addi sp, sp, 16137; RV32I-NEXT: ret138;139; RV64I-LABEL: fsqrt_s:140; RV64I: # %bb.0:141; RV64I-NEXT: addi sp, sp, -16142; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill143; RV64I-NEXT: call sqrtf144; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload145; RV64I-NEXT: addi sp, sp, 16146; RV64I-NEXT: ret147 %1 = call float @llvm.sqrt.f32(float %a)148 ret float %1149}150 151define float @fsgnj_s(float %a, float %b) nounwind {152; CHECKIF-LABEL: fsgnj_s:153; CHECKIF: # %bb.0:154; CHECKIF-NEXT: fsgnj.s fa0, fa0, fa1155; CHECKIF-NEXT: ret156;157; RV32I-LABEL: fsgnj_s:158; RV32I: # %bb.0:159; RV32I-NEXT: lui a2, 524288160; RV32I-NEXT: slli a0, a0, 1161; RV32I-NEXT: srli a0, a0, 1162; RV32I-NEXT: and a1, a1, a2163; RV32I-NEXT: or a0, a0, a1164; RV32I-NEXT: ret165;166; RV64I-LABEL: fsgnj_s:167; RV64I: # %bb.0:168; RV64I-NEXT: lui a2, 524288169; RV64I-NEXT: slli a0, a0, 33170; RV64I-NEXT: srli a0, a0, 33171; RV64I-NEXT: and a1, a1, a2172; RV64I-NEXT: or a0, a0, a1173; RV64I-NEXT: ret174 %1 = call float @llvm.copysign.f32(float %a, float %b)175 ret float %1176}177 178define i32 @fneg_s(float %a, float %b) nounwind {179; CHECKIF-LABEL: fneg_s:180; CHECKIF: # %bb.0:181; CHECKIF-NEXT: fadd.s fa5, fa0, fa0182; CHECKIF-NEXT: fneg.s fa4, fa5183; CHECKIF-NEXT: feq.s a0, fa5, fa4184; CHECKIF-NEXT: ret185;186; RV32I-LABEL: fneg_s:187; RV32I: # %bb.0:188; RV32I-NEXT: addi sp, sp, -16189; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill190; RV32I-NEXT: mv a1, a0191; RV32I-NEXT: call __addsf3192; RV32I-NEXT: lui a1, 524288193; RV32I-NEXT: xor a1, a0, a1194; RV32I-NEXT: call __eqsf2195; RV32I-NEXT: seqz a0, a0196; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload197; RV32I-NEXT: addi sp, sp, 16198; RV32I-NEXT: ret199;200; RV64I-LABEL: fneg_s:201; RV64I: # %bb.0:202; RV64I-NEXT: addi sp, sp, -16203; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill204; RV64I-NEXT: mv a1, a0205; RV64I-NEXT: call __addsf3206; RV64I-NEXT: lui a1, 524288207; RV64I-NEXT: xor a1, a0, a1208; RV64I-NEXT: call __eqsf2209; RV64I-NEXT: sext.w a0, a0210; RV64I-NEXT: seqz a0, a0211; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload212; RV64I-NEXT: addi sp, sp, 16213; RV64I-NEXT: ret214 %1 = fadd float %a, %a215 %2 = fneg float %1216 %3 = fcmp oeq float %1, %2217 %4 = zext i1 %3 to i32218 ret i32 %4219}220 221define float @fsgnjn_s(float %a, float %b) nounwind {222; CHECKIF-LABEL: fsgnjn_s:223; CHECKIF: # %bb.0:224; CHECKIF-NEXT: fadd.s fa5, fa0, fa1225; CHECKIF-NEXT: fsgnjn.s fa0, fa0, fa5226; CHECKIF-NEXT: ret227;228; RV32I-LABEL: fsgnjn_s:229; RV32I: # %bb.0:230; RV32I-NEXT: addi sp, sp, -16231; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill232; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill233; RV32I-NEXT: mv s0, a0234; RV32I-NEXT: call __addsf3235; RV32I-NEXT: lui a1, 524288236; RV32I-NEXT: slli s0, s0, 1237; RV32I-NEXT: xor a0, a0, a1238; RV32I-NEXT: srli s0, s0, 1239; RV32I-NEXT: and a0, a0, a1240; RV32I-NEXT: or a0, s0, a0241; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload242; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload243; RV32I-NEXT: addi sp, sp, 16244; RV32I-NEXT: ret245;246; RV64I-LABEL: fsgnjn_s:247; RV64I: # %bb.0:248; RV64I-NEXT: addi sp, sp, -16249; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill250; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill251; RV64I-NEXT: mv s0, a0252; RV64I-NEXT: call __addsf3253; RV64I-NEXT: lui a1, 524288254; RV64I-NEXT: slli s0, s0, 33255; RV64I-NEXT: xor a0, a0, a1256; RV64I-NEXT: srli s0, s0, 33257; RV64I-NEXT: and a0, a0, a1258; RV64I-NEXT: or a0, s0, a0259; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload260; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload261; RV64I-NEXT: addi sp, sp, 16262; RV64I-NEXT: ret263 %1 = fadd float %a, %b264 %2 = fneg float %1265 %3 = call float @llvm.copysign.f32(float %a, float %2)266 ret float %3267}268 269define float @fabs_s(float %a, float %b) nounwind {270; CHECKIF-LABEL: fabs_s:271; CHECKIF: # %bb.0:272; CHECKIF-NEXT: fadd.s fa5, fa0, fa1273; CHECKIF-NEXT: fabs.s fa4, fa5274; CHECKIF-NEXT: fadd.s fa0, fa4, fa5275; CHECKIF-NEXT: ret276;277; RV32I-LABEL: fabs_s:278; RV32I: # %bb.0:279; RV32I-NEXT: addi sp, sp, -16280; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill281; RV32I-NEXT: call __addsf3282; RV32I-NEXT: mv a1, a0283; RV32I-NEXT: slli a0, a0, 1284; RV32I-NEXT: srli a0, a0, 1285; RV32I-NEXT: call __addsf3286; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload287; RV32I-NEXT: addi sp, sp, 16288; RV32I-NEXT: ret289;290; RV64I-LABEL: fabs_s:291; RV64I: # %bb.0:292; RV64I-NEXT: addi sp, sp, -16293; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill294; RV64I-NEXT: call __addsf3295; RV64I-NEXT: mv a1, a0296; RV64I-NEXT: slli a0, a0, 33297; RV64I-NEXT: srli a0, a0, 33298; RV64I-NEXT: call __addsf3299; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload300; RV64I-NEXT: addi sp, sp, 16301; RV64I-NEXT: ret302 %1 = fadd float %a, %b303 %2 = call float @llvm.fabs.f32(float %1)304 %3 = fadd float %2, %1305 ret float %3306}307 308define float @fminimumnum_s(float %a, float %b) nounwind {309; CHECKIF-LABEL: fminimumnum_s:310; CHECKIF: # %bb.0:311; CHECKIF-NEXT: fmin.s fa0, fa0, fa1312; CHECKIF-NEXT: ret313;314; RV32I-LABEL: fminimumnum_s:315; RV32I: # %bb.0:316; RV32I-NEXT: addi sp, sp, -16317; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill318; RV32I-NEXT: call fminimum_numf319; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload320; RV32I-NEXT: addi sp, sp, 16321; RV32I-NEXT: ret322;323; RV64I-LABEL: fminimumnum_s:324; RV64I: # %bb.0:325; RV64I-NEXT: addi sp, sp, -16326; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill327; RV64I-NEXT: call fminimum_numf328; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload329; RV64I-NEXT: addi sp, sp, 16330; RV64I-NEXT: ret331 %1 = call float @llvm.minimumnum.f32(float %a, float %b)332 ret float %1333}334 335define float @fmaximumnum_s(float %a, float %b) nounwind {336; CHECKIF-LABEL: fmaximumnum_s:337; CHECKIF: # %bb.0:338; CHECKIF-NEXT: fmax.s fa0, fa0, fa1339; CHECKIF-NEXT: ret340;341; RV32I-LABEL: fmaximumnum_s:342; RV32I: # %bb.0:343; RV32I-NEXT: addi sp, sp, -16344; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill345; RV32I-NEXT: call fmaximum_numf346; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload347; RV32I-NEXT: addi sp, sp, 16348; RV32I-NEXT: ret349;350; RV64I-LABEL: fmaximumnum_s:351; RV64I: # %bb.0:352; RV64I-NEXT: addi sp, sp, -16353; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill354; RV64I-NEXT: call fmaximum_numf355; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload356; RV64I-NEXT: addi sp, sp, 16357; RV64I-NEXT: ret358 %1 = call float @llvm.maximumnum.f32(float %a, float %b)359 ret float %1360}361 362define float @fmin_s(float %a, float %b) nounwind {363; CHECKIF-LABEL: fmin_s:364; CHECKIF: # %bb.0:365; CHECKIF-NEXT: fmin.s fa0, fa0, fa1366; CHECKIF-NEXT: ret367;368; RV32I-LABEL: fmin_s:369; RV32I: # %bb.0:370; RV32I-NEXT: addi sp, sp, -16371; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill372; RV32I-NEXT: call fminf373; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload374; RV32I-NEXT: addi sp, sp, 16375; RV32I-NEXT: ret376;377; RV64I-LABEL: fmin_s:378; RV64I: # %bb.0:379; RV64I-NEXT: addi sp, sp, -16380; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill381; RV64I-NEXT: call fminf382; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload383; RV64I-NEXT: addi sp, sp, 16384; RV64I-NEXT: ret385 %1 = call float @llvm.minnum.f32(float %a, float %b)386 ret float %1387}388 389define float @fmax_s(float %a, float %b) nounwind {390; CHECKIF-LABEL: fmax_s:391; CHECKIF: # %bb.0:392; CHECKIF-NEXT: fmax.s fa0, fa0, fa1393; CHECKIF-NEXT: ret394;395; RV32I-LABEL: fmax_s:396; RV32I: # %bb.0:397; RV32I-NEXT: addi sp, sp, -16398; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill399; RV32I-NEXT: call fmaxf400; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload401; RV32I-NEXT: addi sp, sp, 16402; RV32I-NEXT: ret403;404; RV64I-LABEL: fmax_s:405; RV64I: # %bb.0:406; RV64I-NEXT: addi sp, sp, -16407; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill408; RV64I-NEXT: call fmaxf409; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload410; RV64I-NEXT: addi sp, sp, 16411; RV64I-NEXT: ret412 %1 = call float @llvm.maxnum.f32(float %a, float %b)413 ret float %1414}415 416define float @fmadd_s(float %a, float %b, float %c) nounwind {417; CHECKIF-LABEL: fmadd_s:418; CHECKIF: # %bb.0:419; CHECKIF-NEXT: fmadd.s fa0, fa0, fa1, fa2420; CHECKIF-NEXT: ret421;422; RV32I-LABEL: fmadd_s:423; RV32I: # %bb.0:424; RV32I-NEXT: addi sp, sp, -16425; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill426; RV32I-NEXT: call fmaf427; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload428; RV32I-NEXT: addi sp, sp, 16429; RV32I-NEXT: ret430;431; RV64I-LABEL: fmadd_s:432; RV64I: # %bb.0:433; RV64I-NEXT: addi sp, sp, -16434; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill435; RV64I-NEXT: call fmaf436; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload437; RV64I-NEXT: addi sp, sp, 16438; RV64I-NEXT: ret439 %1 = call float @llvm.fma.f32(float %a, float %b, float %c)440 ret float %1441}442 443define float @fmsub_s(float %a, float %b, float %c) nounwind {444; CHECKIF-LABEL: fmsub_s:445; CHECKIF: # %bb.0:446; CHECKIF-NEXT: fmv.w.x fa5, zero447; CHECKIF-NEXT: fadd.s fa5, fa2, fa5448; CHECKIF-NEXT: fmsub.s fa0, fa0, fa1, fa5449; CHECKIF-NEXT: ret450;451; RV32I-LABEL: fmsub_s:452; RV32I: # %bb.0:453; RV32I-NEXT: addi sp, sp, -16454; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill455; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill456; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill457; RV32I-NEXT: mv s0, a0458; RV32I-NEXT: mv s1, a1459; RV32I-NEXT: mv a0, a2460; RV32I-NEXT: li a1, 0461; RV32I-NEXT: call __addsf3462; RV32I-NEXT: lui a2, 524288463; RV32I-NEXT: xor a2, a0, a2464; RV32I-NEXT: mv a0, s0465; RV32I-NEXT: mv a1, s1466; RV32I-NEXT: call fmaf467; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload468; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload469; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload470; RV32I-NEXT: addi sp, sp, 16471; RV32I-NEXT: ret472;473; RV64I-LABEL: fmsub_s:474; RV64I: # %bb.0:475; RV64I-NEXT: addi sp, sp, -32476; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill477; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill478; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill479; RV64I-NEXT: mv s0, a0480; RV64I-NEXT: mv s1, a1481; RV64I-NEXT: mv a0, a2482; RV64I-NEXT: li a1, 0483; RV64I-NEXT: call __addsf3484; RV64I-NEXT: lui a2, 524288485; RV64I-NEXT: xor a2, a0, a2486; RV64I-NEXT: mv a0, s0487; RV64I-NEXT: mv a1, s1488; RV64I-NEXT: call fmaf489; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload490; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload491; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload492; RV64I-NEXT: addi sp, sp, 32493; RV64I-NEXT: ret494 %c_ = fadd float 0.0, %c ; avoid negation using xor495 %negc = fneg float %c_496 %1 = call float @llvm.fma.f32(float %a, float %b, float %negc)497 ret float %1498}499 500define float @fnmadd_s(float %a, float %b, float %c) nounwind {501; CHECKIF-LABEL: fnmadd_s:502; CHECKIF: # %bb.0:503; CHECKIF-NEXT: fmv.w.x fa5, zero504; CHECKIF-NEXT: fadd.s fa4, fa0, fa5505; CHECKIF-NEXT: fadd.s fa5, fa2, fa5506; CHECKIF-NEXT: fnmadd.s fa0, fa4, fa1, fa5507; CHECKIF-NEXT: ret508;509; RV32I-LABEL: fnmadd_s:510; RV32I: # %bb.0:511; RV32I-NEXT: addi sp, sp, -16512; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill513; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill514; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill515; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill516; RV32I-NEXT: mv s0, a1517; RV32I-NEXT: mv s1, a2518; RV32I-NEXT: li a1, 0519; RV32I-NEXT: call __addsf3520; RV32I-NEXT: mv s2, a0521; RV32I-NEXT: mv a0, s1522; RV32I-NEXT: li a1, 0523; RV32I-NEXT: call __addsf3524; RV32I-NEXT: lui a2, 524288525; RV32I-NEXT: xor a1, s2, a2526; RV32I-NEXT: xor a2, a0, a2527; RV32I-NEXT: mv a0, a1528; RV32I-NEXT: mv a1, s0529; RV32I-NEXT: call fmaf530; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload531; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload532; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload533; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload534; RV32I-NEXT: addi sp, sp, 16535; RV32I-NEXT: ret536;537; RV64I-LABEL: fnmadd_s:538; RV64I: # %bb.0:539; RV64I-NEXT: addi sp, sp, -32540; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill541; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill542; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill543; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill544; RV64I-NEXT: mv s0, a1545; RV64I-NEXT: mv s1, a2546; RV64I-NEXT: li a1, 0547; RV64I-NEXT: call __addsf3548; RV64I-NEXT: mv s2, a0549; RV64I-NEXT: mv a0, s1550; RV64I-NEXT: li a1, 0551; RV64I-NEXT: call __addsf3552; RV64I-NEXT: lui a2, 524288553; RV64I-NEXT: xor a1, s2, a2554; RV64I-NEXT: xor a2, a0, a2555; RV64I-NEXT: mv a0, a1556; RV64I-NEXT: mv a1, s0557; RV64I-NEXT: call fmaf558; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload559; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload560; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload561; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload562; RV64I-NEXT: addi sp, sp, 32563; RV64I-NEXT: ret564 %a_ = fadd float 0.0, %a565 %c_ = fadd float 0.0, %c566 %nega = fneg float %a_567 %negc = fneg float %c_568 %1 = call float @llvm.fma.f32(float %nega, float %b, float %negc)569 ret float %1570}571 572define float @fnmadd_s_2(float %a, float %b, float %c) nounwind {573; CHECKIF-LABEL: fnmadd_s_2:574; CHECKIF: # %bb.0:575; CHECKIF-NEXT: fmv.w.x fa5, zero576; CHECKIF-NEXT: fadd.s fa4, fa1, fa5577; CHECKIF-NEXT: fadd.s fa5, fa2, fa5578; CHECKIF-NEXT: fnmadd.s fa0, fa4, fa0, fa5579; CHECKIF-NEXT: ret580;581; RV32I-LABEL: fnmadd_s_2:582; RV32I: # %bb.0:583; RV32I-NEXT: addi sp, sp, -16584; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill585; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill586; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill587; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill588; RV32I-NEXT: mv s0, a0589; RV32I-NEXT: mv a0, a1590; RV32I-NEXT: mv s1, a2591; RV32I-NEXT: li a1, 0592; RV32I-NEXT: call __addsf3593; RV32I-NEXT: mv s2, a0594; RV32I-NEXT: mv a0, s1595; RV32I-NEXT: li a1, 0596; RV32I-NEXT: call __addsf3597; RV32I-NEXT: lui a2, 524288598; RV32I-NEXT: xor a1, s2, a2599; RV32I-NEXT: xor a2, a0, a2600; RV32I-NEXT: mv a0, s0601; RV32I-NEXT: call fmaf602; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload603; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload604; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload605; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload606; RV32I-NEXT: addi sp, sp, 16607; RV32I-NEXT: ret608;609; RV64I-LABEL: fnmadd_s_2:610; RV64I: # %bb.0:611; RV64I-NEXT: addi sp, sp, -32612; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill613; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill614; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill615; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill616; RV64I-NEXT: mv s0, a0617; RV64I-NEXT: mv a0, a1618; RV64I-NEXT: mv s1, a2619; RV64I-NEXT: li a1, 0620; RV64I-NEXT: call __addsf3621; RV64I-NEXT: mv s2, a0622; RV64I-NEXT: mv a0, s1623; RV64I-NEXT: li a1, 0624; RV64I-NEXT: call __addsf3625; RV64I-NEXT: lui a2, 524288626; RV64I-NEXT: xor a1, s2, a2627; RV64I-NEXT: xor a2, a0, a2628; RV64I-NEXT: mv a0, s0629; RV64I-NEXT: call fmaf630; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload631; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload632; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload633; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload634; RV64I-NEXT: addi sp, sp, 32635; RV64I-NEXT: ret636 %b_ = fadd float 0.0, %b637 %c_ = fadd float 0.0, %c638 %negb = fneg float %b_639 %negc = fneg float %c_640 %1 = call float @llvm.fma.f32(float %a, float %negb, float %negc)641 ret float %1642}643 644define float @fnmadd_s_3(float %a, float %b, float %c) nounwind {645; RV32IF-LABEL: fnmadd_s_3:646; RV32IF: # %bb.0:647; RV32IF-NEXT: fmadd.s ft0, fa0, fa1, fa2648; RV32IF-NEXT: fneg.s fa0, ft0649; RV32IF-NEXT: ret650;651; RV64IF-LABEL: fnmadd_s_3:652; RV64IF: # %bb.0:653; RV64IF-NEXT: fmadd.s ft0, fa0, fa1, fa2654; RV64IF-NEXT: fneg.s fa0, ft0655; RV64IF-NEXT: ret656;657; CHECKIF-LABEL: fnmadd_s_3:658; CHECKIF: # %bb.0:659; CHECKIF-NEXT: fmadd.s fa5, fa0, fa1, fa2660; CHECKIF-NEXT: fneg.s fa0, fa5661; CHECKIF-NEXT: ret662;663; RV32I-LABEL: fnmadd_s_3:664; RV32I: # %bb.0:665; RV32I-NEXT: addi sp, sp, -16666; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill667; RV32I-NEXT: call fmaf668; RV32I-NEXT: lui a1, 524288669; RV32I-NEXT: xor a0, a0, a1670; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload671; RV32I-NEXT: addi sp, sp, 16672; RV32I-NEXT: ret673;674; RV64I-LABEL: fnmadd_s_3:675; RV64I: # %bb.0:676; RV64I-NEXT: addi sp, sp, -16677; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill678; RV64I-NEXT: call fmaf679; RV64I-NEXT: lui a1, 524288680; RV64I-NEXT: xor a0, a0, a1681; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload682; RV64I-NEXT: addi sp, sp, 16683; RV64I-NEXT: ret684 %1 = call float @llvm.fma.f32(float %a, float %b, float %c)685 %neg = fneg float %1686 ret float %neg687}688 689define float @fnmadd_nsz(float %a, float %b, float %c) nounwind {690; RV32IF-LABEL: fnmadd_nsz:691; RV32IF: # %bb.0:692; RV32IF-NEXT: fnmadd.s fa0, fa0, fa1, fa2693; RV32IF-NEXT: ret694;695; RV64IF-LABEL: fnmadd_nsz:696; RV64IF: # %bb.0:697; RV64IF-NEXT: fnmadd.s fa0, fa0, fa1, fa2698; RV64IF-NEXT: ret699;700; CHECKIF-LABEL: fnmadd_nsz:701; CHECKIF: # %bb.0:702; CHECKIF-NEXT: fmadd.s fa5, fa0, fa1, fa2703; CHECKIF-NEXT: fneg.s fa0, fa5704; CHECKIF-NEXT: ret705;706; RV32I-LABEL: fnmadd_nsz:707; RV32I: # %bb.0:708; RV32I-NEXT: addi sp, sp, -16709; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill710; RV32I-NEXT: call fmaf711; RV32I-NEXT: lui a1, 524288712; RV32I-NEXT: xor a0, a0, a1713; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload714; RV32I-NEXT: addi sp, sp, 16715; RV32I-NEXT: ret716;717; RV64I-LABEL: fnmadd_nsz:718; RV64I: # %bb.0:719; RV64I-NEXT: addi sp, sp, -16720; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill721; RV64I-NEXT: call fmaf722; RV64I-NEXT: lui a1, 524288723; RV64I-NEXT: xor a0, a0, a1724; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload725; RV64I-NEXT: addi sp, sp, 16726; RV64I-NEXT: ret727 %1 = call nsz float @llvm.fma.f32(float %a, float %b, float %c)728 %neg = fneg nsz float %1729 ret float %neg730}731 732define float @fnmsub_s(float %a, float %b, float %c) nounwind {733; CHECKIF-LABEL: fnmsub_s:734; CHECKIF: # %bb.0:735; CHECKIF-NEXT: fmv.w.x fa5, zero736; CHECKIF-NEXT: fadd.s fa5, fa0, fa5737; CHECKIF-NEXT: fnmsub.s fa0, fa5, fa1, fa2738; CHECKIF-NEXT: ret739;740; RV32I-LABEL: fnmsub_s:741; RV32I: # %bb.0:742; RV32I-NEXT: addi sp, sp, -16743; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill744; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill745; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill746; RV32I-NEXT: mv s0, a1747; RV32I-NEXT: mv s1, a2748; RV32I-NEXT: li a1, 0749; RV32I-NEXT: call __addsf3750; RV32I-NEXT: lui a1, 524288751; RV32I-NEXT: xor a0, a0, a1752; RV32I-NEXT: mv a1, s0753; RV32I-NEXT: mv a2, s1754; RV32I-NEXT: call fmaf755; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload756; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload757; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload758; RV32I-NEXT: addi sp, sp, 16759; RV32I-NEXT: ret760;761; RV64I-LABEL: fnmsub_s:762; RV64I: # %bb.0:763; RV64I-NEXT: addi sp, sp, -32764; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill765; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill766; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill767; RV64I-NEXT: mv s0, a1768; RV64I-NEXT: mv s1, a2769; RV64I-NEXT: li a1, 0770; RV64I-NEXT: call __addsf3771; RV64I-NEXT: lui a1, 524288772; RV64I-NEXT: xor a0, a0, a1773; RV64I-NEXT: mv a1, s0774; RV64I-NEXT: mv a2, s1775; RV64I-NEXT: call fmaf776; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload777; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload778; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload779; RV64I-NEXT: addi sp, sp, 32780; RV64I-NEXT: ret781 %a_ = fadd float 0.0, %a782 %nega = fneg float %a_783 %1 = call float @llvm.fma.f32(float %nega, float %b, float %c)784 ret float %1785}786 787define float @fnmsub_s_2(float %a, float %b, float %c) nounwind {788; CHECKIF-LABEL: fnmsub_s_2:789; CHECKIF: # %bb.0:790; CHECKIF-NEXT: fmv.w.x fa5, zero791; CHECKIF-NEXT: fadd.s fa5, fa1, fa5792; CHECKIF-NEXT: fnmsub.s fa0, fa5, fa0, fa2793; CHECKIF-NEXT: ret794;795; RV32I-LABEL: fnmsub_s_2:796; RV32I: # %bb.0:797; RV32I-NEXT: addi sp, sp, -16798; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill799; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill800; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill801; RV32I-NEXT: mv s0, a0802; RV32I-NEXT: mv a0, a1803; RV32I-NEXT: mv s1, a2804; RV32I-NEXT: li a1, 0805; RV32I-NEXT: call __addsf3806; RV32I-NEXT: lui a1, 524288807; RV32I-NEXT: xor a1, a0, a1808; RV32I-NEXT: mv a0, s0809; RV32I-NEXT: mv a2, s1810; RV32I-NEXT: call fmaf811; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload812; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload813; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload814; RV32I-NEXT: addi sp, sp, 16815; RV32I-NEXT: ret816;817; RV64I-LABEL: fnmsub_s_2:818; RV64I: # %bb.0:819; RV64I-NEXT: addi sp, sp, -32820; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill821; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill822; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill823; RV64I-NEXT: mv s0, a0824; RV64I-NEXT: mv a0, a1825; RV64I-NEXT: mv s1, a2826; RV64I-NEXT: li a1, 0827; RV64I-NEXT: call __addsf3828; RV64I-NEXT: lui a1, 524288829; RV64I-NEXT: xor a1, a0, a1830; RV64I-NEXT: mv a0, s0831; RV64I-NEXT: mv a2, s1832; RV64I-NEXT: call fmaf833; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload834; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload835; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload836; RV64I-NEXT: addi sp, sp, 32837; RV64I-NEXT: ret838 %b_ = fadd float 0.0, %b839 %negb = fneg float %b_840 %1 = call float @llvm.fma.f32(float %a, float %negb, float %c)841 ret float %1842}843 844define float @fmadd_s_contract(float %a, float %b, float %c) nounwind {845; CHECKIF-LABEL: fmadd_s_contract:846; CHECKIF: # %bb.0:847; CHECKIF-NEXT: fmadd.s fa0, fa0, fa1, fa2848; CHECKIF-NEXT: ret849;850; RV32I-LABEL: fmadd_s_contract:851; RV32I: # %bb.0:852; RV32I-NEXT: addi sp, sp, -16853; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill854; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill855; RV32I-NEXT: mv s0, a2856; RV32I-NEXT: call __mulsf3857; RV32I-NEXT: mv a1, s0858; RV32I-NEXT: call __addsf3859; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload860; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload861; RV32I-NEXT: addi sp, sp, 16862; RV32I-NEXT: ret863;864; RV64I-LABEL: fmadd_s_contract:865; RV64I: # %bb.0:866; RV64I-NEXT: addi sp, sp, -16867; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill868; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill869; RV64I-NEXT: mv s0, a2870; RV64I-NEXT: call __mulsf3871; RV64I-NEXT: mv a1, s0872; RV64I-NEXT: call __addsf3873; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload874; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload875; RV64I-NEXT: addi sp, sp, 16876; RV64I-NEXT: ret877 %1 = fmul contract float %a, %b878 %2 = fadd contract float %1, %c879 ret float %2880}881 882define float @fmsub_s_contract(float %a, float %b, float %c) nounwind {883; CHECKIF-LABEL: fmsub_s_contract:884; CHECKIF: # %bb.0:885; CHECKIF-NEXT: fmv.w.x fa5, zero886; CHECKIF-NEXT: fadd.s fa5, fa2, fa5887; CHECKIF-NEXT: fmul.s fa4, fa0, fa1888; CHECKIF-NEXT: fsub.s fa0, fa4, fa5889; CHECKIF-NEXT: ret890;891; RV32I-LABEL: fmsub_s_contract:892; RV32I: # %bb.0:893; RV32I-NEXT: addi sp, sp, -16894; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill895; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill896; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill897; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill898; RV32I-NEXT: mv s0, a0899; RV32I-NEXT: mv s1, a1900; RV32I-NEXT: mv a0, a2901; RV32I-NEXT: li a1, 0902; RV32I-NEXT: call __addsf3903; RV32I-NEXT: mv s2, a0904; RV32I-NEXT: mv a0, s0905; RV32I-NEXT: mv a1, s1906; RV32I-NEXT: call __mulsf3907; RV32I-NEXT: mv a1, s2908; RV32I-NEXT: call __subsf3909; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload910; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload911; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload912; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload913; RV32I-NEXT: addi sp, sp, 16914; RV32I-NEXT: ret915;916; RV64I-LABEL: fmsub_s_contract:917; RV64I: # %bb.0:918; RV64I-NEXT: addi sp, sp, -32919; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill920; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill921; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill922; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill923; RV64I-NEXT: mv s0, a0924; RV64I-NEXT: mv s1, a1925; RV64I-NEXT: mv a0, a2926; RV64I-NEXT: li a1, 0927; RV64I-NEXT: call __addsf3928; RV64I-NEXT: mv s2, a0929; RV64I-NEXT: mv a0, s0930; RV64I-NEXT: mv a1, s1931; RV64I-NEXT: call __mulsf3932; RV64I-NEXT: mv a1, s2933; RV64I-NEXT: call __subsf3934; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload935; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload936; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload937; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload938; RV64I-NEXT: addi sp, sp, 32939; RV64I-NEXT: ret940 %c_ = fadd float 0.0, %c ; avoid negation using xor941 %1 = fmul contract float %a, %b942 %2 = fsub contract float %1, %c_943 ret float %2944}945 946define float @fnmadd_s_contract(float %a, float %b, float %c) nounwind {947; CHECKIF-LABEL: fnmadd_s_contract:948; CHECKIF: # %bb.0:949; CHECKIF-NEXT: fmv.w.x fa5, zero950; CHECKIF-NEXT: fadd.s fa4, fa0, fa5951; CHECKIF-NEXT: fadd.s fa3, fa1, fa5952; CHECKIF-NEXT: fadd.s fa5, fa2, fa5953; CHECKIF-NEXT: fmul.s fa4, fa4, fa3954; CHECKIF-NEXT: fneg.s fa4, fa4955; CHECKIF-NEXT: fsub.s fa0, fa4, fa5956; CHECKIF-NEXT: ret957;958; RV32I-LABEL: fnmadd_s_contract:959; RV32I: # %bb.0:960; RV32I-NEXT: addi sp, sp, -16961; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill962; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill963; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill964; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill965; RV32I-NEXT: mv s0, a1966; RV32I-NEXT: mv s1, a2967; RV32I-NEXT: li a1, 0968; RV32I-NEXT: call __addsf3969; RV32I-NEXT: mv s2, a0970; RV32I-NEXT: mv a0, s0971; RV32I-NEXT: li a1, 0972; RV32I-NEXT: call __addsf3973; RV32I-NEXT: mv s0, a0974; RV32I-NEXT: mv a0, s1975; RV32I-NEXT: li a1, 0976; RV32I-NEXT: call __addsf3977; RV32I-NEXT: mv s1, a0978; RV32I-NEXT: mv a0, s2979; RV32I-NEXT: mv a1, s0980; RV32I-NEXT: call __mulsf3981; RV32I-NEXT: lui a1, 524288982; RV32I-NEXT: xor a0, a0, a1983; RV32I-NEXT: mv a1, s1984; RV32I-NEXT: call __subsf3985; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload986; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload987; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload988; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload989; RV32I-NEXT: addi sp, sp, 16990; RV32I-NEXT: ret991;992; RV64I-LABEL: fnmadd_s_contract:993; RV64I: # %bb.0:994; RV64I-NEXT: addi sp, sp, -32995; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill996; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill997; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill998; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill999; RV64I-NEXT: mv s0, a11000; RV64I-NEXT: mv s1, a21001; RV64I-NEXT: li a1, 01002; RV64I-NEXT: call __addsf31003; RV64I-NEXT: mv s2, a01004; RV64I-NEXT: mv a0, s01005; RV64I-NEXT: li a1, 01006; RV64I-NEXT: call __addsf31007; RV64I-NEXT: mv s0, a01008; RV64I-NEXT: mv a0, s11009; RV64I-NEXT: li a1, 01010; RV64I-NEXT: call __addsf31011; RV64I-NEXT: mv s1, a01012; RV64I-NEXT: mv a0, s21013; RV64I-NEXT: mv a1, s01014; RV64I-NEXT: call __mulsf31015; RV64I-NEXT: lui a1, 5242881016; RV64I-NEXT: xor a0, a0, a11017; RV64I-NEXT: mv a1, s11018; RV64I-NEXT: call __subsf31019; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload1020; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload1021; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload1022; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload1023; RV64I-NEXT: addi sp, sp, 321024; RV64I-NEXT: ret1025 %a_ = fadd float 0.0, %a ; avoid negation using xor1026 %b_ = fadd float 0.0, %b ; avoid negation using xor1027 %c_ = fadd float 0.0, %c ; avoid negation using xor1028 %1 = fmul contract float %a_, %b_1029 %2 = fneg float %11030 %3 = fsub contract float %2, %c_1031 ret float %31032}1033 1034define float @fnmsub_s_contract(float %a, float %b, float %c) nounwind {1035; CHECKIF-LABEL: fnmsub_s_contract:1036; CHECKIF: # %bb.0:1037; CHECKIF-NEXT: fmv.w.x fa5, zero1038; CHECKIF-NEXT: fadd.s fa4, fa0, fa51039; CHECKIF-NEXT: fadd.s fa5, fa1, fa51040; CHECKIF-NEXT: fnmsub.s fa0, fa4, fa5, fa21041; CHECKIF-NEXT: ret1042;1043; RV32I-LABEL: fnmsub_s_contract:1044; RV32I: # %bb.0:1045; RV32I-NEXT: addi sp, sp, -161046; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1047; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill1048; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill1049; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill1050; RV32I-NEXT: mv s0, a11051; RV32I-NEXT: mv s1, a21052; RV32I-NEXT: li a1, 01053; RV32I-NEXT: call __addsf31054; RV32I-NEXT: mv s2, a01055; RV32I-NEXT: mv a0, s01056; RV32I-NEXT: li a1, 01057; RV32I-NEXT: call __addsf31058; RV32I-NEXT: mv a1, a01059; RV32I-NEXT: mv a0, s21060; RV32I-NEXT: call __mulsf31061; RV32I-NEXT: mv a1, a01062; RV32I-NEXT: mv a0, s11063; RV32I-NEXT: call __subsf31064; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1065; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload1066; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload1067; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload1068; RV32I-NEXT: addi sp, sp, 161069; RV32I-NEXT: ret1070;1071; RV64I-LABEL: fnmsub_s_contract:1072; RV64I: # %bb.0:1073; RV64I-NEXT: addi sp, sp, -321074; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill1075; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill1076; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill1077; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill1078; RV64I-NEXT: mv s0, a11079; RV64I-NEXT: mv s1, a21080; RV64I-NEXT: li a1, 01081; RV64I-NEXT: call __addsf31082; RV64I-NEXT: mv s2, a01083; RV64I-NEXT: mv a0, s01084; RV64I-NEXT: li a1, 01085; RV64I-NEXT: call __addsf31086; RV64I-NEXT: mv a1, a01087; RV64I-NEXT: mv a0, s21088; RV64I-NEXT: call __mulsf31089; RV64I-NEXT: mv a1, a01090; RV64I-NEXT: mv a0, s11091; RV64I-NEXT: call __subsf31092; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload1093; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload1094; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload1095; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload1096; RV64I-NEXT: addi sp, sp, 321097; RV64I-NEXT: ret1098 %a_ = fadd float 0.0, %a ; avoid negation using xor1099 %b_ = fadd float 0.0, %b ; avoid negation using xor1100 %1 = fmul contract float %a_, %b_1101 %2 = fsub contract float %c, %11102 ret float %21103}1104 1105define float @fsgnjx_f32(float %x, float %y) nounwind {1106; CHECKIF-LABEL: fsgnjx_f32:1107; CHECKIF: # %bb.0:1108; CHECKIF-NEXT: lui a0, 2600961109; CHECKIF-NEXT: fmv.w.x fa5, a01110; CHECKIF-NEXT: fsgnj.s fa5, fa5, fa01111; CHECKIF-NEXT: fmul.s fa0, fa5, fa11112; CHECKIF-NEXT: ret1113;1114; RV32I-LABEL: fsgnjx_f32:1115; RV32I: # %bb.0:1116; RV32I-NEXT: addi sp, sp, -161117; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1118; RV32I-NEXT: lui a2, 5242881119; RV32I-NEXT: lui a3, 2600961120; RV32I-NEXT: and a0, a0, a21121; RV32I-NEXT: or a0, a0, a31122; RV32I-NEXT: call __mulsf31123; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1124; RV32I-NEXT: addi sp, sp, 161125; RV32I-NEXT: ret1126;1127; RV64I-LABEL: fsgnjx_f32:1128; RV64I: # %bb.0:1129; RV64I-NEXT: addi sp, sp, -161130; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1131; RV64I-NEXT: lui a2, 5242881132; RV64I-NEXT: lui a3, 2600961133; RV64I-NEXT: and a0, a0, a21134; RV64I-NEXT: or a0, a0, a31135; RV64I-NEXT: call __mulsf31136; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1137; RV64I-NEXT: addi sp, sp, 161138; RV64I-NEXT: ret1139 %z = call float @llvm.copysign.f32(float 1.0, float %x)1140 %mul = fmul float %z, %y1141 ret float %mul1142}1143