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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -global-isel -mattr=+f -verify-machineinstrs < %s \3; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIF,RV32IF %s4; RUN: llc -mtriple=riscv64 -global-isel -mattr=+f -verify-machineinstrs < %s \5; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECKIF,RV64IF %s6; RUN: llc -mtriple=riscv32 -global-isel -verify-machineinstrs < %s \7; RUN: | FileCheck -check-prefix=RV32I %s8; RUN: llc -mtriple=riscv64 -global-isel -verify-machineinstrs < %s \9; RUN: | FileCheck -check-prefix=RV64I %s10 11define i32 @fcvt_w_s(float %a) nounwind {12; CHECKIF-LABEL: fcvt_w_s:13; CHECKIF: # %bb.0:14; CHECKIF-NEXT: fcvt.w.s a0, fa0, rtz15; CHECKIF-NEXT: ret16;17; RV32I-LABEL: fcvt_w_s:18; RV32I: # %bb.0:19; RV32I-NEXT: addi sp, sp, -1620; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill21; RV32I-NEXT: call __fixsfsi22; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload23; RV32I-NEXT: addi sp, sp, 1624; RV32I-NEXT: ret25;26; RV64I-LABEL: fcvt_w_s:27; RV64I: # %bb.0:28; RV64I-NEXT: addi sp, sp, -1629; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill30; RV64I-NEXT: call __fixsfsi31; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload32; RV64I-NEXT: addi sp, sp, 1633; RV64I-NEXT: ret34 %1 = fptosi float %a to i3235 ret i32 %136}37 38define i32 @fcvt_wu_s(float %a) nounwind {39; CHECKIF-LABEL: fcvt_wu_s:40; CHECKIF: # %bb.0:41; CHECKIF-NEXT: fcvt.wu.s a0, fa0, rtz42; CHECKIF-NEXT: ret43;44; RV32I-LABEL: fcvt_wu_s:45; RV32I: # %bb.0:46; RV32I-NEXT: addi sp, sp, -1647; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill48; RV32I-NEXT: call __fixunssfsi49; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload50; RV32I-NEXT: addi sp, sp, 1651; RV32I-NEXT: ret52;53; RV64I-LABEL: fcvt_wu_s:54; RV64I: # %bb.0:55; RV64I-NEXT: addi sp, sp, -1656; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill57; RV64I-NEXT: call __fixunssfsi58; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload59; RV64I-NEXT: addi sp, sp, 1660; RV64I-NEXT: ret61 %1 = fptoui float %a to i3262 ret i32 %163}64 65; Test where the fptoui has multiple uses, one of which causes a sext to be66; inserted on RV64.67define i32 @fcvt_wu_s_multiple_use(float %x, ptr %y) nounwind {68; CHECKIF-LABEL: fcvt_wu_s_multiple_use:69; CHECKIF: # %bb.0:70; CHECKIF-NEXT: fcvt.wu.s a0, fa0, rtz71; CHECKIF-NEXT: bnez a0, .LBB2_272; CHECKIF-NEXT: # %bb.1:73; CHECKIF-NEXT: li a0, 174; CHECKIF-NEXT: .LBB2_2:75; CHECKIF-NEXT: ret76;77; RV32I-LABEL: fcvt_wu_s_multiple_use:78; RV32I: # %bb.0:79; RV32I-NEXT: addi sp, sp, -1680; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill81; RV32I-NEXT: call __fixunssfsi82; RV32I-NEXT: bnez a0, .LBB2_283; RV32I-NEXT: # %bb.1:84; RV32I-NEXT: li a0, 185; RV32I-NEXT: .LBB2_2:86; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload87; RV32I-NEXT: addi sp, sp, 1688; RV32I-NEXT: ret89;90; RV64I-LABEL: fcvt_wu_s_multiple_use:91; RV64I: # %bb.0:92; RV64I-NEXT: addi sp, sp, -1693; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill94; RV64I-NEXT: call __fixunssfsi95; RV64I-NEXT: sext.w a1, a096; RV64I-NEXT: bnez a1, .LBB2_297; RV64I-NEXT: # %bb.1:98; RV64I-NEXT: li a0, 199; RV64I-NEXT: .LBB2_2:100; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload101; RV64I-NEXT: addi sp, sp, 16102; RV64I-NEXT: ret103 %a = fptoui float %x to i32104 %b = icmp eq i32 %a, 0105 %c = select i1 %b, i32 1, i32 %a106 ret i32 %c107}108 109define signext i32 @fmv_x_w(float %a, float %b) nounwind {110; RV32IF-LABEL: fmv_x_w:111; RV32IF: # %bb.0:112; RV32IF-NEXT: fadd.s fa5, fa0, fa1113; RV32IF-NEXT: fmv.x.w a0, fa5114; RV32IF-NEXT: ret115;116; RV64IF-LABEL: fmv_x_w:117; RV64IF: # %bb.0:118; RV64IF-NEXT: fadd.s fa5, fa0, fa1119; RV64IF-NEXT: fmv.x.w a0, fa5120; RV64IF-NEXT: sext.w a0, a0121; RV64IF-NEXT: ret122;123; RV32I-LABEL: fmv_x_w:124; RV32I: # %bb.0:125; RV32I-NEXT: addi sp, sp, -16126; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill127; RV32I-NEXT: call __addsf3128; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload129; RV32I-NEXT: addi sp, sp, 16130; RV32I-NEXT: ret131;132; RV64I-LABEL: fmv_x_w:133; RV64I: # %bb.0:134; RV64I-NEXT: addi sp, sp, -16135; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill136; RV64I-NEXT: call __addsf3137; RV64I-NEXT: sext.w a0, a0138; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload139; RV64I-NEXT: addi sp, sp, 16140; RV64I-NEXT: ret141; Ensure fmv.x.w is generated even for a soft float calling convention142 %1 = fadd float %a, %b143 %2 = bitcast float %1 to i32144 ret i32 %2145}146 147define float @fcvt_s_w(i32 %a) nounwind {148; CHECKIF-LABEL: fcvt_s_w:149; CHECKIF: # %bb.0:150; CHECKIF-NEXT: fcvt.s.w fa0, a0151; CHECKIF-NEXT: ret152;153; RV32I-LABEL: fcvt_s_w:154; RV32I: # %bb.0:155; RV32I-NEXT: addi sp, sp, -16156; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill157; RV32I-NEXT: call __floatsisf158; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload159; RV32I-NEXT: addi sp, sp, 16160; RV32I-NEXT: ret161;162; RV64I-LABEL: fcvt_s_w:163; RV64I: # %bb.0:164; RV64I-NEXT: addi sp, sp, -16165; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill166; RV64I-NEXT: sext.w a0, a0167; RV64I-NEXT: call __floatsisf168; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload169; RV64I-NEXT: addi sp, sp, 16170; RV64I-NEXT: ret171 %1 = sitofp i32 %a to float172 ret float %1173}174 175define float @fcvt_s_w_load(ptr %p) nounwind {176; CHECKIF-LABEL: fcvt_s_w_load:177; CHECKIF: # %bb.0:178; CHECKIF-NEXT: lw a0, 0(a0)179; CHECKIF-NEXT: fcvt.s.w fa0, a0180; CHECKIF-NEXT: ret181;182; RV32I-LABEL: fcvt_s_w_load:183; RV32I: # %bb.0:184; RV32I-NEXT: addi sp, sp, -16185; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill186; RV32I-NEXT: lw a0, 0(a0)187; RV32I-NEXT: call __floatsisf188; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload189; RV32I-NEXT: addi sp, sp, 16190; RV32I-NEXT: ret191;192; RV64I-LABEL: fcvt_s_w_load:193; RV64I: # %bb.0:194; RV64I-NEXT: addi sp, sp, -16195; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill196; RV64I-NEXT: lw a0, 0(a0)197; RV64I-NEXT: call __floatsisf198; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload199; RV64I-NEXT: addi sp, sp, 16200; RV64I-NEXT: ret201 %a = load i32, ptr %p202 %1 = sitofp i32 %a to float203 ret float %1204}205 206define float @fcvt_s_wu(i32 %a) nounwind {207; CHECKIF-LABEL: fcvt_s_wu:208; CHECKIF: # %bb.0:209; CHECKIF-NEXT: fcvt.s.wu fa0, a0210; CHECKIF-NEXT: ret211;212; RV32I-LABEL: fcvt_s_wu:213; RV32I: # %bb.0:214; RV32I-NEXT: addi sp, sp, -16215; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill216; RV32I-NEXT: call __floatunsisf217; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload218; RV32I-NEXT: addi sp, sp, 16219; RV32I-NEXT: ret220;221; RV64I-LABEL: fcvt_s_wu:222; RV64I: # %bb.0:223; RV64I-NEXT: addi sp, sp, -16224; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill225; RV64I-NEXT: sext.w a0, a0226; RV64I-NEXT: call __floatunsisf227; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload228; RV64I-NEXT: addi sp, sp, 16229; RV64I-NEXT: ret230 %1 = uitofp i32 %a to float231 ret float %1232}233 234define float @fcvt_s_wu_load(ptr %p) nounwind {235; CHECKIF-LABEL: fcvt_s_wu_load:236; CHECKIF: # %bb.0:237; CHECKIF-NEXT: lw a0, 0(a0)238; CHECKIF-NEXT: fcvt.s.wu fa0, a0239; CHECKIF-NEXT: ret240;241; RV32I-LABEL: fcvt_s_wu_load:242; RV32I: # %bb.0:243; RV32I-NEXT: addi sp, sp, -16244; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill245; RV32I-NEXT: lw a0, 0(a0)246; RV32I-NEXT: call __floatunsisf247; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload248; RV32I-NEXT: addi sp, sp, 16249; RV32I-NEXT: ret250;251; RV64I-LABEL: fcvt_s_wu_load:252; RV64I: # %bb.0:253; RV64I-NEXT: addi sp, sp, -16254; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill255; RV64I-NEXT: lw a0, 0(a0)256; RV64I-NEXT: call __floatunsisf257; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload258; RV64I-NEXT: addi sp, sp, 16259; RV64I-NEXT: ret260 %a = load i32, ptr %p261 %1 = uitofp i32 %a to float262 ret float %1263}264 265define float @fmv_w_x(i32 %a, i32 %b) nounwind {266; CHECKIF-LABEL: fmv_w_x:267; CHECKIF: # %bb.0:268; CHECKIF-NEXT: fmv.w.x fa5, a0269; CHECKIF-NEXT: fmv.w.x fa4, a1270; CHECKIF-NEXT: fadd.s fa0, fa5, fa4271; CHECKIF-NEXT: ret272;273; RV32I-LABEL: fmv_w_x:274; RV32I: # %bb.0:275; RV32I-NEXT: addi sp, sp, -16276; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill277; RV32I-NEXT: call __addsf3278; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload279; RV32I-NEXT: addi sp, sp, 16280; RV32I-NEXT: ret281;282; RV64I-LABEL: fmv_w_x:283; RV64I: # %bb.0:284; RV64I-NEXT: addi sp, sp, -16285; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill286; RV64I-NEXT: call __addsf3287; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload288; RV64I-NEXT: addi sp, sp, 16289; RV64I-NEXT: ret290; Ensure fmv.w.x is generated even for a soft float calling convention291 %1 = bitcast i32 %a to float292 %2 = bitcast i32 %b to float293 %3 = fadd float %1, %2294 ret float %3295}296 297define i64 @fcvt_l_s(float %a) nounwind {298; RV32IF-LABEL: fcvt_l_s:299; RV32IF: # %bb.0:300; RV32IF-NEXT: addi sp, sp, -16301; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill302; RV32IF-NEXT: call __fixsfdi303; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload304; RV32IF-NEXT: addi sp, sp, 16305; RV32IF-NEXT: ret306;307; RV64IF-LABEL: fcvt_l_s:308; RV64IF: # %bb.0:309; RV64IF-NEXT: fcvt.l.s a0, fa0, rtz310; RV64IF-NEXT: ret311;312; RV32I-LABEL: fcvt_l_s:313; RV32I: # %bb.0:314; RV32I-NEXT: addi sp, sp, -16315; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill316; RV32I-NEXT: call __fixsfdi317; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload318; RV32I-NEXT: addi sp, sp, 16319; RV32I-NEXT: ret320;321; RV64I-LABEL: fcvt_l_s:322; RV64I: # %bb.0:323; RV64I-NEXT: addi sp, sp, -16324; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill325; RV64I-NEXT: call __fixsfdi326; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload327; RV64I-NEXT: addi sp, sp, 16328; RV64I-NEXT: ret329 %1 = fptosi float %a to i64330 ret i64 %1331}332 333define i64 @fcvt_lu_s(float %a) nounwind {334; RV32IF-LABEL: fcvt_lu_s:335; RV32IF: # %bb.0:336; RV32IF-NEXT: addi sp, sp, -16337; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill338; RV32IF-NEXT: call __fixunssfdi339; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload340; RV32IF-NEXT: addi sp, sp, 16341; RV32IF-NEXT: ret342;343; RV64IF-LABEL: fcvt_lu_s:344; RV64IF: # %bb.0:345; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz346; RV64IF-NEXT: ret347;348; RV32I-LABEL: fcvt_lu_s:349; RV32I: # %bb.0:350; RV32I-NEXT: addi sp, sp, -16351; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill352; RV32I-NEXT: call __fixunssfdi353; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload354; RV32I-NEXT: addi sp, sp, 16355; RV32I-NEXT: ret356;357; RV64I-LABEL: fcvt_lu_s:358; RV64I: # %bb.0:359; RV64I-NEXT: addi sp, sp, -16360; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill361; RV64I-NEXT: call __fixunssfdi362; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload363; RV64I-NEXT: addi sp, sp, 16364; RV64I-NEXT: ret365 %1 = fptoui float %a to i64366 ret i64 %1367}368 369define float @fcvt_s_l(i64 %a) nounwind {370; RV32IF-LABEL: fcvt_s_l:371; RV32IF: # %bb.0:372; RV32IF-NEXT: addi sp, sp, -16373; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill374; RV32IF-NEXT: call __floatdisf375; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload376; RV32IF-NEXT: addi sp, sp, 16377; RV32IF-NEXT: ret378;379; RV64IF-LABEL: fcvt_s_l:380; RV64IF: # %bb.0:381; RV64IF-NEXT: fcvt.s.l fa0, a0382; RV64IF-NEXT: ret383;384; RV32I-LABEL: fcvt_s_l:385; RV32I: # %bb.0:386; RV32I-NEXT: addi sp, sp, -16387; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill388; RV32I-NEXT: call __floatdisf389; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload390; RV32I-NEXT: addi sp, sp, 16391; RV32I-NEXT: ret392;393; RV64I-LABEL: fcvt_s_l:394; RV64I: # %bb.0:395; RV64I-NEXT: addi sp, sp, -16396; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill397; RV64I-NEXT: call __floatdisf398; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload399; RV64I-NEXT: addi sp, sp, 16400; RV64I-NEXT: ret401 %1 = sitofp i64 %a to float402 ret float %1403}404 405define float @fcvt_s_lu(i64 %a) nounwind {406; RV32IF-LABEL: fcvt_s_lu:407; RV32IF: # %bb.0:408; RV32IF-NEXT: addi sp, sp, -16409; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill410; RV32IF-NEXT: call __floatundisf411; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload412; RV32IF-NEXT: addi sp, sp, 16413; RV32IF-NEXT: ret414;415; RV64IF-LABEL: fcvt_s_lu:416; RV64IF: # %bb.0:417; RV64IF-NEXT: fcvt.s.lu fa0, a0418; RV64IF-NEXT: ret419;420; RV32I-LABEL: fcvt_s_lu:421; RV32I: # %bb.0:422; RV32I-NEXT: addi sp, sp, -16423; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill424; RV32I-NEXT: call __floatundisf425; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload426; RV32I-NEXT: addi sp, sp, 16427; RV32I-NEXT: ret428;429; RV64I-LABEL: fcvt_s_lu:430; RV64I: # %bb.0:431; RV64I-NEXT: addi sp, sp, -16432; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill433; RV64I-NEXT: call __floatundisf434; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload435; RV64I-NEXT: addi sp, sp, 16436; RV64I-NEXT: ret437 %1 = uitofp i64 %a to float438 ret float %1439}440 441define float @fcvt_s_w_i8(i8 signext %a) nounwind {442; CHECKIF-LABEL: fcvt_s_w_i8:443; CHECKIF: # %bb.0:444; CHECKIF-NEXT: fcvt.s.w fa0, a0445; CHECKIF-NEXT: ret446;447; RV32I-LABEL: fcvt_s_w_i8:448; RV32I: # %bb.0:449; RV32I-NEXT: addi sp, sp, -16450; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill451; RV32I-NEXT: call __floatsisf452; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload453; RV32I-NEXT: addi sp, sp, 16454; RV32I-NEXT: ret455;456; RV64I-LABEL: fcvt_s_w_i8:457; RV64I: # %bb.0:458; RV64I-NEXT: addi sp, sp, -16459; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill460; RV64I-NEXT: call __floatsisf461; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload462; RV64I-NEXT: addi sp, sp, 16463; RV64I-NEXT: ret464 %1 = sitofp i8 %a to float465 ret float %1466}467 468define float @fcvt_s_wu_i8(i8 zeroext %a) nounwind {469; CHECKIF-LABEL: fcvt_s_wu_i8:470; CHECKIF: # %bb.0:471; CHECKIF-NEXT: fcvt.s.wu fa0, a0472; CHECKIF-NEXT: ret473;474; RV32I-LABEL: fcvt_s_wu_i8:475; RV32I: # %bb.0:476; RV32I-NEXT: addi sp, sp, -16477; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill478; RV32I-NEXT: call __floatunsisf479; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload480; RV32I-NEXT: addi sp, sp, 16481; RV32I-NEXT: ret482;483; RV64I-LABEL: fcvt_s_wu_i8:484; RV64I: # %bb.0:485; RV64I-NEXT: addi sp, sp, -16486; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill487; RV64I-NEXT: call __floatunsisf488; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload489; RV64I-NEXT: addi sp, sp, 16490; RV64I-NEXT: ret491 %1 = uitofp i8 %a to float492 ret float %1493}494 495define float @fcvt_s_w_i16(i16 signext %a) nounwind {496; CHECKIF-LABEL: fcvt_s_w_i16:497; CHECKIF: # %bb.0:498; CHECKIF-NEXT: fcvt.s.w fa0, a0499; CHECKIF-NEXT: ret500;501; RV32I-LABEL: fcvt_s_w_i16:502; RV32I: # %bb.0:503; RV32I-NEXT: addi sp, sp, -16504; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill505; RV32I-NEXT: call __floatsisf506; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload507; RV32I-NEXT: addi sp, sp, 16508; RV32I-NEXT: ret509;510; RV64I-LABEL: fcvt_s_w_i16:511; RV64I: # %bb.0:512; RV64I-NEXT: addi sp, sp, -16513; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill514; RV64I-NEXT: call __floatsisf515; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload516; RV64I-NEXT: addi sp, sp, 16517; RV64I-NEXT: ret518 %1 = sitofp i16 %a to float519 ret float %1520}521 522define float @fcvt_s_wu_i16(i16 zeroext %a) nounwind {523; CHECKIF-LABEL: fcvt_s_wu_i16:524; CHECKIF: # %bb.0:525; CHECKIF-NEXT: fcvt.s.wu fa0, a0526; CHECKIF-NEXT: ret527;528; RV32I-LABEL: fcvt_s_wu_i16:529; RV32I: # %bb.0:530; RV32I-NEXT: addi sp, sp, -16531; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill532; RV32I-NEXT: call __floatunsisf533; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload534; RV32I-NEXT: addi sp, sp, 16535; RV32I-NEXT: ret536;537; RV64I-LABEL: fcvt_s_wu_i16:538; RV64I: # %bb.0:539; RV64I-NEXT: addi sp, sp, -16540; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill541; RV64I-NEXT: call __floatunsisf542; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload543; RV64I-NEXT: addi sp, sp, 16544; RV64I-NEXT: ret545 %1 = uitofp i16 %a to float546 ret float %1547}548 549; Make sure we select W version of addi on RV64.550define signext i32 @fcvt_s_w_demanded_bits(i32 signext %0, ptr %1) nounwind {551; RV32IF-LABEL: fcvt_s_w_demanded_bits:552; RV32IF: # %bb.0:553; RV32IF-NEXT: addi a0, a0, 1554; RV32IF-NEXT: fcvt.s.w fa5, a0555; RV32IF-NEXT: fsw fa5, 0(a1)556; RV32IF-NEXT: ret557;558; RV64IF-LABEL: fcvt_s_w_demanded_bits:559; RV64IF: # %bb.0:560; RV64IF-NEXT: addiw a0, a0, 1561; RV64IF-NEXT: fcvt.s.w fa5, a0562; RV64IF-NEXT: fsw fa5, 0(a1)563; RV64IF-NEXT: ret564;565; RV32I-LABEL: fcvt_s_w_demanded_bits:566; RV32I: # %bb.0:567; RV32I-NEXT: addi sp, sp, -16568; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill569; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill570; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill571; RV32I-NEXT: mv s0, a1572; RV32I-NEXT: addi s1, a0, 1573; RV32I-NEXT: mv a0, s1574; RV32I-NEXT: call __floatsisf575; RV32I-NEXT: sw a0, 0(s0)576; RV32I-NEXT: mv a0, s1577; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload578; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload579; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload580; RV32I-NEXT: addi sp, sp, 16581; RV32I-NEXT: ret582;583; RV64I-LABEL: fcvt_s_w_demanded_bits:584; RV64I: # %bb.0:585; RV64I-NEXT: addi sp, sp, -32586; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill587; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill588; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill589; RV64I-NEXT: mv s0, a1590; RV64I-NEXT: addiw s1, a0, 1591; RV64I-NEXT: mv a0, s1592; RV64I-NEXT: call __floatsisf593; RV64I-NEXT: sw a0, 0(s0)594; RV64I-NEXT: mv a0, s1595; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload596; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload597; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload598; RV64I-NEXT: addi sp, sp, 32599; RV64I-NEXT: ret600 %3 = add i32 %0, 1601 %4 = sitofp i32 %3 to float602 store float %4, ptr %1, align 4603 ret i32 %3604}605 606; Make sure we select W version of addi on RV64.607define signext i32 @fcvt_s_wu_demanded_bits(i32 signext %0, ptr %1) nounwind {608; RV32IF-LABEL: fcvt_s_wu_demanded_bits:609; RV32IF: # %bb.0:610; RV32IF-NEXT: addi a0, a0, 1611; RV32IF-NEXT: fcvt.s.wu fa5, a0612; RV32IF-NEXT: fsw fa5, 0(a1)613; RV32IF-NEXT: ret614;615; RV64IF-LABEL: fcvt_s_wu_demanded_bits:616; RV64IF: # %bb.0:617; RV64IF-NEXT: addiw a0, a0, 1618; RV64IF-NEXT: fcvt.s.wu fa5, a0619; RV64IF-NEXT: fsw fa5, 0(a1)620; RV64IF-NEXT: ret621;622; RV32I-LABEL: fcvt_s_wu_demanded_bits:623; RV32I: # %bb.0:624; RV32I-NEXT: addi sp, sp, -16625; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill626; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill627; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill628; RV32I-NEXT: mv s0, a1629; RV32I-NEXT: addi s1, a0, 1630; RV32I-NEXT: mv a0, s1631; RV32I-NEXT: call __floatunsisf632; RV32I-NEXT: sw a0, 0(s0)633; RV32I-NEXT: mv a0, s1634; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload635; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload636; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload637; RV32I-NEXT: addi sp, sp, 16638; RV32I-NEXT: ret639;640; RV64I-LABEL: fcvt_s_wu_demanded_bits:641; RV64I: # %bb.0:642; RV64I-NEXT: addi sp, sp, -32643; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill644; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill645; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill646; RV64I-NEXT: mv s0, a1647; RV64I-NEXT: addiw s1, a0, 1648; RV64I-NEXT: mv a0, s1649; RV64I-NEXT: call __floatunsisf650; RV64I-NEXT: sw a0, 0(s0)651; RV64I-NEXT: mv a0, s1652; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload653; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload654; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload655; RV64I-NEXT: addi sp, sp, 32656; RV64I-NEXT: ret657 %3 = add i32 %0, 1658 %4 = uitofp i32 %3 to float659 store float %4, ptr %1, align 4660 ret i32 %3661}662 663define signext i16 @fcvt_w_s_i16(float %a) nounwind {664; RV32IF-LABEL: fcvt_w_s_i16:665; RV32IF: # %bb.0:666; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz667; RV32IF-NEXT: slli a0, a0, 16668; RV32IF-NEXT: srai a0, a0, 16669; RV32IF-NEXT: ret670;671; RV64IF-LABEL: fcvt_w_s_i16:672; RV64IF: # %bb.0:673; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz674; RV64IF-NEXT: slli a0, a0, 48675; RV64IF-NEXT: srai a0, a0, 48676; RV64IF-NEXT: ret677;678; RV32I-LABEL: fcvt_w_s_i16:679; RV32I: # %bb.0:680; RV32I-NEXT: addi sp, sp, -16681; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill682; RV32I-NEXT: call __fixsfsi683; RV32I-NEXT: slli a0, a0, 16684; RV32I-NEXT: srai a0, a0, 16685; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload686; RV32I-NEXT: addi sp, sp, 16687; RV32I-NEXT: ret688;689; RV64I-LABEL: fcvt_w_s_i16:690; RV64I: # %bb.0:691; RV64I-NEXT: addi sp, sp, -16692; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill693; RV64I-NEXT: call __fixsfsi694; RV64I-NEXT: slli a0, a0, 48695; RV64I-NEXT: srai a0, a0, 48696; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload697; RV64I-NEXT: addi sp, sp, 16698; RV64I-NEXT: ret699 %1 = fptosi float %a to i16700 ret i16 %1701}702 703define zeroext i16 @fcvt_wu_s_i16(float %a) nounwind {704; RV32IF-LABEL: fcvt_wu_s_i16:705; RV32IF: # %bb.0:706; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz707; RV32IF-NEXT: slli a0, a0, 16708; RV32IF-NEXT: srli a0, a0, 16709; RV32IF-NEXT: ret710;711; RV64IF-LABEL: fcvt_wu_s_i16:712; RV64IF: # %bb.0:713; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz714; RV64IF-NEXT: slli a0, a0, 48715; RV64IF-NEXT: srli a0, a0, 48716; RV64IF-NEXT: ret717;718; RV32I-LABEL: fcvt_wu_s_i16:719; RV32I: # %bb.0:720; RV32I-NEXT: addi sp, sp, -16721; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill722; RV32I-NEXT: call __fixunssfsi723; RV32I-NEXT: slli a0, a0, 16724; RV32I-NEXT: srli a0, a0, 16725; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload726; RV32I-NEXT: addi sp, sp, 16727; RV32I-NEXT: ret728;729; RV64I-LABEL: fcvt_wu_s_i16:730; RV64I: # %bb.0:731; RV64I-NEXT: addi sp, sp, -16732; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill733; RV64I-NEXT: call __fixunssfsi734; RV64I-NEXT: slli a0, a0, 48735; RV64I-NEXT: srli a0, a0, 48736; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload737; RV64I-NEXT: addi sp, sp, 16738; RV64I-NEXT: ret739 %1 = fptoui float %a to i16740 ret i16 %1741}742 743define signext i8 @fcvt_w_s_i8(float %a) nounwind {744; RV32IF-LABEL: fcvt_w_s_i8:745; RV32IF: # %bb.0:746; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz747; RV32IF-NEXT: slli a0, a0, 24748; RV32IF-NEXT: srai a0, a0, 24749; RV32IF-NEXT: ret750;751; RV64IF-LABEL: fcvt_w_s_i8:752; RV64IF: # %bb.0:753; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz754; RV64IF-NEXT: slli a0, a0, 56755; RV64IF-NEXT: srai a0, a0, 56756; RV64IF-NEXT: ret757;758; RV32I-LABEL: fcvt_w_s_i8:759; RV32I: # %bb.0:760; RV32I-NEXT: addi sp, sp, -16761; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill762; RV32I-NEXT: call __fixsfsi763; RV32I-NEXT: slli a0, a0, 24764; RV32I-NEXT: srai a0, a0, 24765; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload766; RV32I-NEXT: addi sp, sp, 16767; RV32I-NEXT: ret768;769; RV64I-LABEL: fcvt_w_s_i8:770; RV64I: # %bb.0:771; RV64I-NEXT: addi sp, sp, -16772; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill773; RV64I-NEXT: call __fixsfsi774; RV64I-NEXT: slli a0, a0, 56775; RV64I-NEXT: srai a0, a0, 56776; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload777; RV64I-NEXT: addi sp, sp, 16778; RV64I-NEXT: ret779 %1 = fptosi float %a to i8780 ret i8 %1781}782 783define zeroext i8 @fcvt_wu_s_i8(float %a) nounwind {784; CHECKIF-LABEL: fcvt_wu_s_i8:785; CHECKIF: # %bb.0:786; CHECKIF-NEXT: fcvt.wu.s a0, fa0, rtz787; CHECKIF-NEXT: zext.b a0, a0788; CHECKIF-NEXT: ret789;790; RV32I-LABEL: fcvt_wu_s_i8:791; RV32I: # %bb.0:792; RV32I-NEXT: addi sp, sp, -16793; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill794; RV32I-NEXT: call __fixunssfsi795; RV32I-NEXT: zext.b a0, a0796; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload797; RV32I-NEXT: addi sp, sp, 16798; RV32I-NEXT: ret799;800; RV64I-LABEL: fcvt_wu_s_i8:801; RV64I: # %bb.0:802; RV64I-NEXT: addi sp, sp, -16803; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill804; RV64I-NEXT: call __fixunssfsi805; RV64I-NEXT: zext.b a0, a0806; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload807; RV64I-NEXT: addi sp, sp, 16808; RV64I-NEXT: ret809 %1 = fptoui float %a to i8810 ret i8 %1811}812