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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -global-isel -verify-machineinstrs < %s \3; RUN: | FileCheck %s --check-prefix=RV32I4; RUN: llc -mtriple=riscv32 -global-isel -mattr=+zbb -verify-machineinstrs < %s \5; RUN: | FileCheck %s --check-prefix=RV32ZBB6; RUN: llc -mtriple=riscv64 -global-isel -verify-machineinstrs < %s \7; RUN: | FileCheck %s --check-prefix=RV64I8; RUN: llc -mtriple=riscv64 -global-isel -mattr=+zbb -verify-machineinstrs < %s \9; RUN: | FileCheck %s --check-prefix=RV64ZBB10 11define i8 @abs8(i8 %x) {12; RV32I-LABEL: abs8:13; RV32I: # %bb.0:14; RV32I-NEXT: slli a1, a0, 2415; RV32I-NEXT: srai a1, a1, 3116; RV32I-NEXT: add a0, a0, a117; RV32I-NEXT: xor a0, a0, a118; RV32I-NEXT: ret19;20; RV32ZBB-LABEL: abs8:21; RV32ZBB: # %bb.0:22; RV32ZBB-NEXT: sext.b a0, a023; RV32ZBB-NEXT: neg a1, a024; RV32ZBB-NEXT: max a0, a0, a125; RV32ZBB-NEXT: ret26;27; RV64I-LABEL: abs8:28; RV64I: # %bb.0:29; RV64I-NEXT: slli a1, a0, 5630; RV64I-NEXT: srai a1, a1, 6331; RV64I-NEXT: add a0, a0, a132; RV64I-NEXT: xor a0, a0, a133; RV64I-NEXT: ret34;35; RV64ZBB-LABEL: abs8:36; RV64ZBB: # %bb.0:37; RV64ZBB-NEXT: sext.b a0, a038; RV64ZBB-NEXT: neg a1, a039; RV64ZBB-NEXT: max a0, a0, a140; RV64ZBB-NEXT: ret41 %abs = tail call i8 @llvm.abs.i8(i8 %x, i1 true)42 ret i8 %abs43}44 45define i16 @abs16(i16 %x) {46; RV32I-LABEL: abs16:47; RV32I: # %bb.0:48; RV32I-NEXT: slli a1, a0, 1649; RV32I-NEXT: srai a1, a1, 3150; RV32I-NEXT: add a0, a0, a151; RV32I-NEXT: xor a0, a0, a152; RV32I-NEXT: ret53;54; RV32ZBB-LABEL: abs16:55; RV32ZBB: # %bb.0:56; RV32ZBB-NEXT: sext.h a0, a057; RV32ZBB-NEXT: neg a1, a058; RV32ZBB-NEXT: max a0, a0, a159; RV32ZBB-NEXT: ret60;61; RV64I-LABEL: abs16:62; RV64I: # %bb.0:63; RV64I-NEXT: slli a1, a0, 4864; RV64I-NEXT: srai a1, a1, 6365; RV64I-NEXT: add a0, a0, a166; RV64I-NEXT: xor a0, a0, a167; RV64I-NEXT: ret68;69; RV64ZBB-LABEL: abs16:70; RV64ZBB: # %bb.0:71; RV64ZBB-NEXT: sext.h a0, a072; RV64ZBB-NEXT: neg a1, a073; RV64ZBB-NEXT: max a0, a0, a174; RV64ZBB-NEXT: ret75 %abs = tail call i16 @llvm.abs.i16(i16 %x, i1 true)76 ret i16 %abs77}78 79define i32 @abs32(i32 %x) {80; RV32I-LABEL: abs32:81; RV32I: # %bb.0:82; RV32I-NEXT: srai a1, a0, 3183; RV32I-NEXT: add a0, a0, a184; RV32I-NEXT: xor a0, a0, a185; RV32I-NEXT: ret86;87; RV32ZBB-LABEL: abs32:88; RV32ZBB: # %bb.0:89; RV32ZBB-NEXT: neg a1, a090; RV32ZBB-NEXT: max a0, a0, a191; RV32ZBB-NEXT: ret92;93; RV64I-LABEL: abs32:94; RV64I: # %bb.0:95; RV64I-NEXT: sraiw a1, a0, 3196; RV64I-NEXT: addw a0, a0, a197; RV64I-NEXT: xor a0, a0, a198; RV64I-NEXT: ret99;100; RV64ZBB-LABEL: abs32:101; RV64ZBB: # %bb.0:102; RV64ZBB-NEXT: sext.w a0, a0103; RV64ZBB-NEXT: neg a1, a0104; RV64ZBB-NEXT: max a0, a0, a1105; RV64ZBB-NEXT: ret106 %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)107 ret i32 %abs108}109 110define i64 @abs64(i64 %x) {111; RV32I-LABEL: abs64:112; RV32I: # %bb.0:113; RV32I-NEXT: srai a2, a1, 31114; RV32I-NEXT: add a0, a0, a2115; RV32I-NEXT: add a1, a1, a2116; RV32I-NEXT: sltu a3, a0, a2117; RV32I-NEXT: add a1, a1, a3118; RV32I-NEXT: xor a0, a0, a2119; RV32I-NEXT: xor a1, a1, a2120; RV32I-NEXT: ret121;122; RV32ZBB-LABEL: abs64:123; RV32ZBB: # %bb.0:124; RV32ZBB-NEXT: srai a2, a1, 31125; RV32ZBB-NEXT: add a0, a0, a2126; RV32ZBB-NEXT: add a1, a1, a2127; RV32ZBB-NEXT: sltu a3, a0, a2128; RV32ZBB-NEXT: add a1, a1, a3129; RV32ZBB-NEXT: xor a0, a0, a2130; RV32ZBB-NEXT: xor a1, a1, a2131; RV32ZBB-NEXT: ret132;133; RV64I-LABEL: abs64:134; RV64I: # %bb.0:135; RV64I-NEXT: srai a1, a0, 63136; RV64I-NEXT: add a0, a0, a1137; RV64I-NEXT: xor a0, a0, a1138; RV64I-NEXT: ret139;140; RV64ZBB-LABEL: abs64:141; RV64ZBB: # %bb.0:142; RV64ZBB-NEXT: neg a1, a0143; RV64ZBB-NEXT: max a0, a0, a1144; RV64ZBB-NEXT: ret145 %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)146 ret i64 %abs147}148