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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \3# RUN: | FileCheck -check-prefix=RV32I %s4 5---6name: add_i8_signext7legalized: true8regBankSelected: true9tracksRegLiveness: true10body: |11 bb.0.entry:12 liveins: $x10, $x1113 14 ; RV32I-LABEL: name: add_i8_signext15 ; RV32I: liveins: $x10, $x1116 ; RV32I-NEXT: {{ $}}17 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1018 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x1119 ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY1]]20 ; RV32I-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADD]], 2421 ; RV32I-NEXT: [[SRAI:%[0-9]+]]:gpr = SRAI [[SLLI]], 2422 ; RV32I-NEXT: $x10 = COPY [[SRAI]]23 ; RV32I-NEXT: PseudoRET implicit $x1024 %0:gprb(s32) = COPY $x1025 %1:gprb(s32) = COPY $x1126 %2:gprb(s32) = G_ADD %0, %127 %3:gprb(s32) = G_CONSTANT i32 2428 %4:gprb(s32) = G_SHL %2, %3(s32)29 %5:gprb(s32) = G_ASHR %4, %3(s32)30 $x10 = COPY %5(s32)31 PseudoRET implicit $x1032 33...34---35name: add_i8_zeroext36legalized: true37regBankSelected: true38tracksRegLiveness: true39body: |40 bb.0.entry:41 liveins: $x10, $x1142 43 ; RV32I-LABEL: name: add_i8_zeroext44 ; RV32I: liveins: $x10, $x1145 ; RV32I-NEXT: {{ $}}46 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1047 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x1148 ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY1]]49 ; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[ADD]], 25550 ; RV32I-NEXT: $x10 = COPY [[ANDI]]51 ; RV32I-NEXT: PseudoRET implicit $x1052 %0:gprb(s32) = COPY $x1053 %1:gprb(s32) = COPY $x1154 %2:gprb(s32) = G_ADD %0, %155 %3:gprb(s32) = G_CONSTANT i32 25556 %4:gprb(s32) = G_AND %2, %357 $x10 = COPY %4(s32)58 PseudoRET implicit $x1059 60...61---62name: add_i16_signext63legalized: true64regBankSelected: true65tracksRegLiveness: true66body: |67 bb.0.entry:68 liveins: $x10, $x1169 70 ; RV32I-LABEL: name: add_i16_signext71 ; RV32I: liveins: $x10, $x1172 ; RV32I-NEXT: {{ $}}73 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1074 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x1175 ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY1]]76 ; RV32I-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADD]], 1677 ; RV32I-NEXT: [[SRAI:%[0-9]+]]:gpr = SRAI [[SLLI]], 1678 ; RV32I-NEXT: $x10 = COPY [[SRAI]]79 ; RV32I-NEXT: PseudoRET implicit $x1080 %0:gprb(s32) = COPY $x1081 %1:gprb(s32) = COPY $x1182 %2:gprb(s32) = G_ADD %0, %183 %3:gprb(s32) = G_CONSTANT i32 1684 %4:gprb(s32) = G_SHL %2, %3(s32)85 %5:gprb(s32) = G_ASHR %4, %3(s32)86 $x10 = COPY %5(s32)87 PseudoRET implicit $x1088 89...90---91name: add_i16_zeroext92legalized: true93regBankSelected: true94tracksRegLiveness: true95body: |96 bb.0.entry:97 liveins: $x10, $x1198 99 ; RV32I-LABEL: name: add_i16_zeroext100 ; RV32I: liveins: $x10, $x11101 ; RV32I-NEXT: {{ $}}102 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10103 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11104 ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY1]]105 ; RV32I-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADD]], 16106 ; RV32I-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[SLLI]], 16107 ; RV32I-NEXT: $x10 = COPY [[SRLI]]108 ; RV32I-NEXT: PseudoRET implicit $x10109 %0:gprb(s32) = COPY $x10110 %1:gprb(s32) = COPY $x11111 %2:gprb(s32) = G_ADD %0, %1112 %3:gprb(s32) = G_CONSTANT i32 65535113 %4:gprb(s32) = G_AND %2, %3114 $x10 = COPY %4(s32)115 PseudoRET implicit $x10116 117...118---119name: add_i32120legalized: true121regBankSelected: true122tracksRegLiveness: true123body: |124 bb.0.entry:125 liveins: $x10, $x11126 127 ; RV32I-LABEL: name: add_i32128 ; RV32I: liveins: $x10, $x11129 ; RV32I-NEXT: {{ $}}130 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10131 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11132 ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY1]]133 ; RV32I-NEXT: $x10 = COPY [[ADD]]134 ; RV32I-NEXT: PseudoRET implicit $x10135 %0:gprb(s32) = COPY $x10136 %1:gprb(s32) = COPY $x11137 %2:gprb(s32) = G_ADD %0, %1138 $x10 = COPY %2(s32)139 PseudoRET implicit $x10140 141...142---143name: addi_i32144legalized: true145regBankSelected: true146tracksRegLiveness: true147body: |148 bb.0.entry:149 liveins: $x10150 151 ; RV32I-LABEL: name: addi_i32152 ; RV32I: liveins: $x10153 ; RV32I-NEXT: {{ $}}154 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10155 ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY]], 1234156 ; RV32I-NEXT: $x10 = COPY [[ADDI]]157 ; RV32I-NEXT: PseudoRET implicit $x10158 %0:gprb(s32) = COPY $x10159 %1:gprb(s32) = G_CONSTANT i32 1234160 %2:gprb(s32) = G_ADD %0, %1161 $x10 = COPY %2(s32)162 PseudoRET implicit $x10163 164...165---166name: sub_i32167legalized: true168regBankSelected: true169tracksRegLiveness: true170body: |171 bb.0.entry:172 liveins: $x10, $x11173 174 ; RV32I-LABEL: name: sub_i32175 ; RV32I: liveins: $x10, $x11176 ; RV32I-NEXT: {{ $}}177 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10178 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11179 ; RV32I-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY]], [[COPY1]]180 ; RV32I-NEXT: $x10 = COPY [[SUB]]181 ; RV32I-NEXT: PseudoRET implicit $x10182 %0:gprb(s32) = COPY $x10183 %1:gprb(s32) = COPY $x11184 %2:gprb(s32) = G_SUB %0, %1185 $x10 = COPY %2(s32)186 PseudoRET implicit $x10187 188...189---190name: subi_i32191legalized: true192regBankSelected: true193tracksRegLiveness: true194body: |195 bb.0.entry:196 liveins: $x10197 198 ; RV32I-LABEL: name: subi_i32199 ; RV32I: liveins: $x10200 ; RV32I-NEXT: {{ $}}201 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10202 ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1234203 ; RV32I-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY]], [[ADDI]]204 ; RV32I-NEXT: $x10 = COPY [[SUB]]205 ; RV32I-NEXT: PseudoRET implicit $x10206 %0:gprb(s32) = COPY $x10207 %1:gprb(s32) = G_CONSTANT i32 -1234208 %2:gprb(s32) = G_SUB %0, %1209 $x10 = COPY %2(s32)210 PseudoRET implicit $x10211 212...213---214name: sll_i32215legalized: true216regBankSelected: true217tracksRegLiveness: true218body: |219 bb.0.entry:220 liveins: $x10, $x11221 222 ; RV32I-LABEL: name: sll_i32223 ; RV32I: liveins: $x10, $x11224 ; RV32I-NEXT: {{ $}}225 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10226 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11227 ; RV32I-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[COPY1]]228 ; RV32I-NEXT: $x10 = COPY [[SLL]]229 ; RV32I-NEXT: PseudoRET implicit $x10230 %0:gprb(s32) = COPY $x10231 %1:gprb(s32) = COPY $x11232 %2:gprb(s32) = G_SHL %0, %1233 $x10 = COPY %2(s32)234 PseudoRET implicit $x10235 236...237---238name: slli_i32239legalized: true240regBankSelected: true241tracksRegLiveness: true242body: |243 bb.0.entry:244 liveins: $x10245 246 ; RV32I-LABEL: name: slli_i32247 ; RV32I: liveins: $x10248 ; RV32I-NEXT: {{ $}}249 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10250 ; RV32I-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY]], 31251 ; RV32I-NEXT: $x10 = COPY [[SLLI]]252 ; RV32I-NEXT: PseudoRET implicit $x10253 %0:gprb(s32) = COPY $x10254 %1:gprb(s32) = G_CONSTANT i32 31255 %2:gprb(s32) = G_SHL %0, %1256 $x10 = COPY %2(s32)257 PseudoRET implicit $x10258 259...260---261name: sra_i32262legalized: true263regBankSelected: true264tracksRegLiveness: true265body: |266 bb.0.entry:267 liveins: $x10, $x11268 269 ; RV32I-LABEL: name: sra_i32270 ; RV32I: liveins: $x10, $x11271 ; RV32I-NEXT: {{ $}}272 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10273 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11274 ; RV32I-NEXT: [[SRA:%[0-9]+]]:gpr = SRA [[COPY]], [[COPY1]]275 ; RV32I-NEXT: $x10 = COPY [[SRA]]276 ; RV32I-NEXT: PseudoRET implicit $x10277 %0:gprb(s32) = COPY $x10278 %1:gprb(s32) = COPY $x11279 %2:gprb(s32) = G_ASHR %0, %1280 $x10 = COPY %2(s32)281 PseudoRET implicit $x10282 283...284---285name: srai_i32286legalized: true287regBankSelected: true288tracksRegLiveness: true289body: |290 bb.0.entry:291 liveins: $x10292 293 ; RV32I-LABEL: name: srai_i32294 ; RV32I: liveins: $x10295 ; RV32I-NEXT: {{ $}}296 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10297 ; RV32I-NEXT: [[SRAI:%[0-9]+]]:gpr = SRAI [[COPY]], 31298 ; RV32I-NEXT: $x10 = COPY [[SRAI]]299 ; RV32I-NEXT: PseudoRET implicit $x10300 %0:gprb(s32) = COPY $x10301 %1:gprb(s32) = G_CONSTANT i32 31302 %2:gprb(s32) = G_ASHR %0, %1303 $x10 = COPY %2(s32)304 PseudoRET implicit $x10305 306...307---308name: srl_i32309legalized: true310regBankSelected: true311tracksRegLiveness: true312body: |313 bb.0.entry:314 liveins: $x10, $x11315 316 ; RV32I-LABEL: name: srl_i32317 ; RV32I: liveins: $x10, $x11318 ; RV32I-NEXT: {{ $}}319 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10320 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11321 ; RV32I-NEXT: [[SRL:%[0-9]+]]:gpr = SRL [[COPY]], [[COPY1]]322 ; RV32I-NEXT: $x10 = COPY [[SRL]]323 ; RV32I-NEXT: PseudoRET implicit $x10324 %0:gprb(s32) = COPY $x10325 %1:gprb(s32) = COPY $x11326 %2:gprb(s32) = G_LSHR %0, %1327 $x10 = COPY %2(s32)328 PseudoRET implicit $x10329 330...331---332name: srli_i32333legalized: true334regBankSelected: true335tracksRegLiveness: true336body: |337 bb.0.entry:338 liveins: $x10339 340 ; RV32I-LABEL: name: srli_i32341 ; RV32I: liveins: $x10342 ; RV32I-NEXT: {{ $}}343 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10344 ; RV32I-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[COPY]], 31345 ; RV32I-NEXT: $x10 = COPY [[SRLI]]346 ; RV32I-NEXT: PseudoRET implicit $x10347 %0:gprb(s32) = COPY $x10348 %1:gprb(s32) = G_CONSTANT i32 31349 %2:gprb(s32) = G_LSHR %0, %1350 $x10 = COPY %2(s32)351 PseudoRET implicit $x10352 353...354---355name: and_i32356legalized: true357regBankSelected: true358tracksRegLiveness: true359body: |360 bb.0.entry:361 liveins: $x10, $x11362 363 ; RV32I-LABEL: name: and_i32364 ; RV32I: liveins: $x10, $x11365 ; RV32I-NEXT: {{ $}}366 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10367 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11368 ; RV32I-NEXT: [[AND:%[0-9]+]]:gpr = AND [[COPY]], [[COPY1]]369 ; RV32I-NEXT: $x10 = COPY [[AND]]370 ; RV32I-NEXT: PseudoRET implicit $x10371 %0:gprb(s32) = COPY $x10372 %1:gprb(s32) = COPY $x11373 %2:gprb(s32) = G_AND %0, %1374 $x10 = COPY %2(s32)375 PseudoRET implicit $x10376 377...378---379name: andi_i32380legalized: true381regBankSelected: true382tracksRegLiveness: true383body: |384 bb.0.entry:385 liveins: $x10386 387 ; RV32I-LABEL: name: andi_i32388 ; RV32I: liveins: $x10389 ; RV32I-NEXT: {{ $}}390 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10391 ; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 1234392 ; RV32I-NEXT: $x10 = COPY [[ANDI]]393 ; RV32I-NEXT: PseudoRET implicit $x10394 %0:gprb(s32) = COPY $x10395 %1:gprb(s32) = G_CONSTANT i32 1234396 %2:gprb(s32) = G_AND %0, %1397 $x10 = COPY %2(s32)398 PseudoRET implicit $x10399 400...401---402name: or_i32403legalized: true404regBankSelected: true405tracksRegLiveness: true406body: |407 bb.0.entry:408 liveins: $x10, $x11409 410 ; RV32I-LABEL: name: or_i32411 ; RV32I: liveins: $x10, $x11412 ; RV32I-NEXT: {{ $}}413 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10414 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11415 ; RV32I-NEXT: [[OR:%[0-9]+]]:gpr = OR [[COPY]], [[COPY1]]416 ; RV32I-NEXT: $x10 = COPY [[OR]]417 ; RV32I-NEXT: PseudoRET implicit $x10418 %0:gprb(s32) = COPY $x10419 %1:gprb(s32) = COPY $x11420 %2:gprb(s32) = G_OR %0, %1421 $x10 = COPY %2(s32)422 PseudoRET implicit $x10423 424...425---426name: ori_i32427legalized: true428regBankSelected: true429tracksRegLiveness: true430body: |431 bb.0.entry:432 liveins: $x10433 434 ; RV32I-LABEL: name: ori_i32435 ; RV32I: liveins: $x10436 ; RV32I-NEXT: {{ $}}437 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10438 ; RV32I-NEXT: [[ORI:%[0-9]+]]:gpr = ORI [[COPY]], 1234439 ; RV32I-NEXT: $x10 = COPY [[ORI]]440 ; RV32I-NEXT: PseudoRET implicit $x10441 %0:gprb(s32) = COPY $x10442 %1:gprb(s32) = G_CONSTANT i32 1234443 %2:gprb(s32) = G_OR %0, %1444 $x10 = COPY %2(s32)445 PseudoRET implicit $x10446 447...448---449name: xor_i32450legalized: true451regBankSelected: true452tracksRegLiveness: true453body: |454 bb.0.entry:455 liveins: $x10, $x11456 457 ; RV32I-LABEL: name: xor_i32458 ; RV32I: liveins: $x10, $x11459 ; RV32I-NEXT: {{ $}}460 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10461 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11462 ; RV32I-NEXT: [[XOR:%[0-9]+]]:gpr = XOR [[COPY]], [[COPY1]]463 ; RV32I-NEXT: $x10 = COPY [[XOR]]464 ; RV32I-NEXT: PseudoRET implicit $x10465 %0:gprb(s32) = COPY $x10466 %1:gprb(s32) = COPY $x11467 %2:gprb(s32) = G_XOR %0, %1468 $x10 = COPY %2(s32)469 PseudoRET implicit $x10470 471...472---473name: xori_i32474legalized: true475regBankSelected: true476tracksRegLiveness: true477body: |478 bb.0.entry:479 liveins: $x10480 481 ; RV32I-LABEL: name: xori_i32482 ; RV32I: liveins: $x10483 ; RV32I-NEXT: {{ $}}484 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10485 ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[COPY]], 1234486 ; RV32I-NEXT: $x10 = COPY [[XORI]]487 ; RV32I-NEXT: PseudoRET implicit $x10488 %0:gprb(s32) = COPY $x10489 %1:gprb(s32) = G_CONSTANT i32 1234490 %2:gprb(s32) = G_XOR %0, %1491 $x10 = COPY %2(s32)492 PseudoRET implicit $x10493 494...495---496name: add_i64497legalized: true498regBankSelected: true499tracksRegLiveness: true500body: |501 bb.0.entry:502 liveins: $x10, $x11, $x12, $x13503 504 ; RV32I-LABEL: name: add_i64505 ; RV32I: liveins: $x10, $x11, $x12, $x13506 ; RV32I-NEXT: {{ $}}507 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10508 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11509 ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12510 ; RV32I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x13511 ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY2]]512 ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[ADD]], [[COPY2]]513 ; RV32I-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[COPY1]], [[COPY3]]514 ; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[SLTU]], 1515 ; RV32I-NEXT: [[ADD2:%[0-9]+]]:gpr = ADD [[ADD1]], [[ANDI]]516 ; RV32I-NEXT: $x10 = COPY [[ADD]]517 ; RV32I-NEXT: $x11 = COPY [[ADD2]]518 ; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11519 %0:gprb(s32) = COPY $x10520 %1:gprb(s32) = COPY $x11521 %2:gprb(s32) = COPY $x12522 %3:gprb(s32) = COPY $x13523 %4:gprb(s32) = G_ADD %0, %2524 %5:gprb(s32) = G_ICMP intpred(ult), %4(s32), %2525 %6:gprb(s32) = G_ADD %1, %3526 %7:gprb(s32) = G_CONSTANT i32 1527 %8:gprb(s32) = G_AND %5, %7528 %9:gprb(s32) = G_ADD %6, %8529 $x10 = COPY %4(s32)530 $x11 = COPY %9(s32)531 PseudoRET implicit $x10, implicit $x11532 533...534---535name: sub_i64536legalized: true537regBankSelected: true538tracksRegLiveness: true539body: |540 bb.0.entry:541 liveins: $x10, $x11, $x12, $x13542 543 ; RV32I-LABEL: name: sub_i64544 ; RV32I: liveins: $x10, $x11, $x12, $x13545 ; RV32I-NEXT: {{ $}}546 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10547 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11548 ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12549 ; RV32I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x13550 ; RV32I-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY]], [[COPY2]]551 ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY]], [[COPY2]]552 ; RV32I-NEXT: [[SUB1:%[0-9]+]]:gpr = SUB [[COPY1]], [[COPY3]]553 ; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[SLTU]], 1554 ; RV32I-NEXT: [[SUB2:%[0-9]+]]:gpr = SUB [[SUB1]], [[ANDI]]555 ; RV32I-NEXT: $x10 = COPY [[SUB]]556 ; RV32I-NEXT: $x11 = COPY [[SUB2]]557 ; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11558 %0:gprb(s32) = COPY $x10559 %1:gprb(s32) = COPY $x11560 %2:gprb(s32) = COPY $x12561 %3:gprb(s32) = COPY $x13562 %4:gprb(s32) = G_SUB %0, %2563 %5:gprb(s32) = G_ICMP intpred(ult), %0(s32), %2564 %6:gprb(s32) = G_SUB %1, %3565 %7:gprb(s32) = G_CONSTANT i32 1566 %8:gprb(s32) = G_AND %5, %7567 %9:gprb(s32) = G_SUB %6, %8568 $x10 = COPY %4(s32)569 $x11 = COPY %9(s32)570 PseudoRET implicit $x10, implicit $x11571 572...573