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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=riscv32 -mattr=+m -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \3# RUN: | FileCheck -check-prefix=RV32I %s4 5---6name: mul_i327legalized: true8regBankSelected: true9tracksRegLiveness: true10body: |11 bb.0.entry:12 liveins: $x10, $x1113 14 ; RV32I-LABEL: name: mul_i3215 ; RV32I: liveins: $x10, $x1116 ; RV32I-NEXT: {{ $}}17 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1018 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x1119 ; RV32I-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[COPY]], [[COPY1]]20 ; RV32I-NEXT: $x10 = COPY [[MUL]]21 ; RV32I-NEXT: PseudoRET implicit $x1022 %0:gprb(s32) = COPY $x1023 %1:gprb(s32) = COPY $x1124 %2:gprb(s32) = G_MUL %0, %125 $x10 = COPY %2(s32)26 PseudoRET implicit $x1027 28...29---30name: sdiv_i3231legalized: true32regBankSelected: true33tracksRegLiveness: true34body: |35 bb.0.entry:36 liveins: $x10, $x1137 38 ; RV32I-LABEL: name: sdiv_i3239 ; RV32I: liveins: $x10, $x1140 ; RV32I-NEXT: {{ $}}41 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1042 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x1143 ; RV32I-NEXT: [[DIV:%[0-9]+]]:gpr = DIV [[COPY]], [[COPY1]]44 ; RV32I-NEXT: $x10 = COPY [[DIV]]45 ; RV32I-NEXT: PseudoRET implicit $x1046 %0:gprb(s32) = COPY $x1047 %1:gprb(s32) = COPY $x1148 %2:gprb(s32) = G_SDIV %0, %149 $x10 = COPY %2(s32)50 PseudoRET implicit $x1051 52...53---54name: srem_i3255legalized: true56regBankSelected: true57tracksRegLiveness: true58body: |59 bb.0.entry:60 liveins: $x10, $x1161 62 ; RV32I-LABEL: name: srem_i3263 ; RV32I: liveins: $x10, $x1164 ; RV32I-NEXT: {{ $}}65 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1066 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x1167 ; RV32I-NEXT: [[REM:%[0-9]+]]:gpr = REM [[COPY]], [[COPY1]]68 ; RV32I-NEXT: $x10 = COPY [[REM]]69 ; RV32I-NEXT: PseudoRET implicit $x1070 %0:gprb(s32) = COPY $x1071 %1:gprb(s32) = COPY $x1172 %2:gprb(s32) = G_SREM %0, %173 $x10 = COPY %2(s32)74 PseudoRET implicit $x1075 76...77---78name: smulh_i3279legalized: true80regBankSelected: true81tracksRegLiveness: true82body: |83 bb.0.entry:84 liveins: $x10, $x1185 86 ; RV32I-LABEL: name: smulh_i3287 ; RV32I: liveins: $x10, $x1188 ; RV32I-NEXT: {{ $}}89 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1090 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x1191 ; RV32I-NEXT: [[MULH:%[0-9]+]]:gpr = MULH [[COPY]], [[COPY1]]92 ; RV32I-NEXT: $x10 = COPY [[MULH]]93 ; RV32I-NEXT: PseudoRET implicit $x1094 %0:gprb(s32) = COPY $x1095 %1:gprb(s32) = COPY $x1196 %2:gprb(s32) = G_SMULH %0, %197 $x10 = COPY %2(s32)98 PseudoRET implicit $x1099 100...101---102name: udiv_i32103legalized: true104regBankSelected: true105tracksRegLiveness: true106body: |107 bb.0.entry:108 liveins: $x10, $x11109 110 ; RV32I-LABEL: name: udiv_i32111 ; RV32I: liveins: $x10, $x11112 ; RV32I-NEXT: {{ $}}113 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10114 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11115 ; RV32I-NEXT: [[DIVU:%[0-9]+]]:gpr = DIVU [[COPY]], [[COPY1]]116 ; RV32I-NEXT: $x10 = COPY [[DIVU]]117 ; RV32I-NEXT: PseudoRET implicit $x10118 %0:gprb(s32) = COPY $x10119 %1:gprb(s32) = COPY $x11120 %2:gprb(s32) = G_UDIV %0, %1121 $x10 = COPY %2(s32)122 PseudoRET implicit $x10123 124...125---126name: urem_i32127legalized: true128regBankSelected: true129tracksRegLiveness: true130body: |131 bb.0.entry:132 liveins: $x10, $x11133 134 ; RV32I-LABEL: name: urem_i32135 ; RV32I: liveins: $x10, $x11136 ; RV32I-NEXT: {{ $}}137 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10138 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11139 ; RV32I-NEXT: [[REMU:%[0-9]+]]:gpr = REMU [[COPY]], [[COPY1]]140 ; RV32I-NEXT: $x10 = COPY [[REMU]]141 ; RV32I-NEXT: PseudoRET implicit $x10142 %0:gprb(s32) = COPY $x10143 %1:gprb(s32) = COPY $x11144 %2:gprb(s32) = G_UREM %0, %1145 $x10 = COPY %2(s32)146 PseudoRET implicit $x10147 148...149---150name: mul_i64151legalized: true152regBankSelected: true153tracksRegLiveness: true154body: |155 bb.0.entry:156 liveins: $x10, $x11, $x12, $x13157 158 ; RV32I-LABEL: name: mul_i64159 ; RV32I: liveins: $x10, $x11, $x12, $x13160 ; RV32I-NEXT: {{ $}}161 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10162 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11163 ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12164 ; RV32I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x13165 ; RV32I-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[COPY]], [[COPY2]]166 ; RV32I-NEXT: [[MUL1:%[0-9]+]]:gpr = MUL [[COPY1]], [[COPY2]]167 ; RV32I-NEXT: [[MUL2:%[0-9]+]]:gpr = MUL [[COPY]], [[COPY3]]168 ; RV32I-NEXT: [[MULHU:%[0-9]+]]:gpr = MULHU [[COPY]], [[COPY2]]169 ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[MUL1]], [[MUL2]]170 ; RV32I-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[ADD]], [[MULHU]]171 ; RV32I-NEXT: $x10 = COPY [[MUL]]172 ; RV32I-NEXT: $x11 = COPY [[ADD1]]173 ; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11174 %0:gprb(s32) = COPY $x10175 %1:gprb(s32) = COPY $x11176 %2:gprb(s32) = COPY $x12177 %3:gprb(s32) = COPY $x13178 %4:gprb(s32) = G_MUL %0, %2179 %5:gprb(s32) = G_MUL %1, %2180 %6:gprb(s32) = G_MUL %0, %3181 %7:gprb(s32) = G_UMULH %0, %2182 %8:gprb(s32) = G_ADD %5, %6183 %9:gprb(s32) = G_ADD %8, %7184 $x10 = COPY %4(s32)185 $x11 = COPY %9(s32)186 PseudoRET implicit $x10, implicit $x11187 188...189