261 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=riscv64 -mattr=+m -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \3# RUN: | FileCheck -check-prefix=RV64I %s4 5---6name: sdiv_i327legalized: true8regBankSelected: true9tracksRegLiveness: true10body: |11 bb.0.entry:12 liveins: $x10, $x1113 14 ; RV64I-LABEL: name: sdiv_i3215 ; RV64I: liveins: $x10, $x1116 ; RV64I-NEXT: {{ $}}17 ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1018 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x1119 ; RV64I-NEXT: [[DIVW:%[0-9]+]]:gpr = DIVW [[COPY]], [[COPY1]]20 ; RV64I-NEXT: $x10 = COPY [[DIVW]]21 ; RV64I-NEXT: PseudoRET implicit $x1022 %0:gprb(s64) = COPY $x1023 %1:gprb(s64) = COPY $x1124 %2:gprb(s64) = G_DIVW %0, %125 $x10 = COPY %2(s64)26 PseudoRET implicit $x1027 28...29---30name: udiv_i3231legalized: true32regBankSelected: true33tracksRegLiveness: true34body: |35 bb.0.entry:36 liveins: $x10, $x1137 38 ; RV64I-LABEL: name: udiv_i3239 ; RV64I: liveins: $x10, $x1140 ; RV64I-NEXT: {{ $}}41 ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1042 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x1143 ; RV64I-NEXT: [[DIVUW:%[0-9]+]]:gpr = DIVUW [[COPY]], [[COPY1]]44 ; RV64I-NEXT: $x10 = COPY [[DIVUW]]45 ; RV64I-NEXT: PseudoRET implicit $x1046 %0:gprb(s64) = COPY $x1047 %1:gprb(s64) = COPY $x1148 %2:gprb(s64) = G_DIVUW %0, %149 $x10 = COPY %2(s64)50 PseudoRET implicit $x1051 52...53---54name: urem_i3255legalized: true56regBankSelected: true57tracksRegLiveness: true58body: |59 bb.0.entry:60 liveins: $x10, $x1161 62 ; RV64I-LABEL: name: urem_i3263 ; RV64I: liveins: $x10, $x1164 ; RV64I-NEXT: {{ $}}65 ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1066 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x1167 ; RV64I-NEXT: [[REMUW:%[0-9]+]]:gpr = REMUW [[COPY]], [[COPY1]]68 ; RV64I-NEXT: $x10 = COPY [[REMUW]]69 ; RV64I-NEXT: PseudoRET implicit $x1070 %0:gprb(s64) = COPY $x1071 %1:gprb(s64) = COPY $x1172 %2:gprb(s64) = G_REMUW %0, %173 $x10 = COPY %2(s64)74 PseudoRET implicit $x1075 76...77---78name: mul_i6479legalized: true80regBankSelected: true81tracksRegLiveness: true82body: |83 bb.0.entry:84 liveins: $x10, $x1185 86 ; RV64I-LABEL: name: mul_i6487 ; RV64I: liveins: $x10, $x1188 ; RV64I-NEXT: {{ $}}89 ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1090 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x1191 ; RV64I-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[COPY]], [[COPY1]]92 ; RV64I-NEXT: $x10 = COPY [[MUL]]93 ; RV64I-NEXT: PseudoRET implicit $x1094 %0:gprb(s64) = COPY $x1095 %1:gprb(s64) = COPY $x1196 %2:gprb(s64) = G_MUL %0, %197 $x10 = COPY %2(s64)98 PseudoRET implicit $x1099 100...101---102name: sdiv_i64103legalized: true104regBankSelected: true105tracksRegLiveness: true106body: |107 bb.0.entry:108 liveins: $x10, $x11109 110 ; RV64I-LABEL: name: sdiv_i64111 ; RV64I: liveins: $x10, $x11112 ; RV64I-NEXT: {{ $}}113 ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10114 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11115 ; RV64I-NEXT: [[DIV:%[0-9]+]]:gpr = DIV [[COPY]], [[COPY1]]116 ; RV64I-NEXT: $x10 = COPY [[DIV]]117 ; RV64I-NEXT: PseudoRET implicit $x10118 %0:gprb(s64) = COPY $x10119 %1:gprb(s64) = COPY $x11120 %2:gprb(s64) = G_SDIV %0, %1121 $x10 = COPY %2(s64)122 PseudoRET implicit $x10123 124...125---126name: srem_i64127legalized: true128regBankSelected: true129tracksRegLiveness: true130body: |131 bb.0.entry:132 liveins: $x10, $x11133 134 ; RV64I-LABEL: name: srem_i64135 ; RV64I: liveins: $x10, $x11136 ; RV64I-NEXT: {{ $}}137 ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10138 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11139 ; RV64I-NEXT: [[REM:%[0-9]+]]:gpr = REM [[COPY]], [[COPY1]]140 ; RV64I-NEXT: $x10 = COPY [[REM]]141 ; RV64I-NEXT: PseudoRET implicit $x10142 %0:gprb(s64) = COPY $x10143 %1:gprb(s64) = COPY $x11144 %2:gprb(s64) = G_SREM %0, %1145 $x10 = COPY %2(s64)146 PseudoRET implicit $x10147 148...149---150name: smulh_i64151legalized: true152regBankSelected: true153tracksRegLiveness: true154body: |155 bb.0.entry:156 liveins: $x10, $x11157 158 ; RV64I-LABEL: name: smulh_i64159 ; RV64I: liveins: $x10, $x11160 ; RV64I-NEXT: {{ $}}161 ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10162 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11163 ; RV64I-NEXT: [[MULH:%[0-9]+]]:gpr = MULH [[COPY]], [[COPY1]]164 ; RV64I-NEXT: $x10 = COPY [[MULH]]165 ; RV64I-NEXT: PseudoRET implicit $x10166 %0:gprb(s64) = COPY $x10167 %1:gprb(s64) = COPY $x11168 %2:gprb(s64) = G_SMULH %0, %1169 $x10 = COPY %2(s64)170 PseudoRET implicit $x10171 172...173---174name: udiv_i64175legalized: true176regBankSelected: true177tracksRegLiveness: true178body: |179 bb.0.entry:180 liveins: $x10, $x11181 182 ; RV64I-LABEL: name: udiv_i64183 ; RV64I: liveins: $x10, $x11184 ; RV64I-NEXT: {{ $}}185 ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10186 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11187 ; RV64I-NEXT: [[DIVU:%[0-9]+]]:gpr = DIVU [[COPY]], [[COPY1]]188 ; RV64I-NEXT: $x10 = COPY [[DIVU]]189 ; RV64I-NEXT: PseudoRET implicit $x10190 %0:gprb(s64) = COPY $x10191 %1:gprb(s64) = COPY $x11192 %2:gprb(s64) = G_UDIV %0, %1193 $x10 = COPY %2(s64)194 PseudoRET implicit $x10195 196...197---198name: urem_i64199legalized: true200regBankSelected: true201tracksRegLiveness: true202body: |203 bb.0.entry:204 liveins: $x10, $x11205 206 ; RV64I-LABEL: name: urem_i64207 ; RV64I: liveins: $x10, $x11208 ; RV64I-NEXT: {{ $}}209 ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10210 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11211 ; RV64I-NEXT: [[REMU:%[0-9]+]]:gpr = REMU [[COPY]], [[COPY1]]212 ; RV64I-NEXT: $x10 = COPY [[REMU]]213 ; RV64I-NEXT: PseudoRET implicit $x10214 %0:gprb(s64) = COPY $x10215 %1:gprb(s64) = COPY $x11216 %2:gprb(s64) = G_UREM %0, %1217 $x10 = COPY %2(s64)218 PseudoRET implicit $x10219 220...221---222name: mul_i128223legalized: true224regBankSelected: true225tracksRegLiveness: true226body: |227 bb.0.entry:228 liveins: $x10, $x11, $x12, $x13229 230 ; RV64I-LABEL: name: mul_i128231 ; RV64I: liveins: $x10, $x11, $x12, $x13232 ; RV64I-NEXT: {{ $}}233 ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10234 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11235 ; RV64I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12236 ; RV64I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x13237 ; RV64I-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[COPY]], [[COPY2]]238 ; RV64I-NEXT: [[MUL1:%[0-9]+]]:gpr = MUL [[COPY1]], [[COPY2]]239 ; RV64I-NEXT: [[MUL2:%[0-9]+]]:gpr = MUL [[COPY]], [[COPY3]]240 ; RV64I-NEXT: [[MULHU:%[0-9]+]]:gpr = MULHU [[COPY]], [[COPY2]]241 ; RV64I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[MUL1]], [[MUL2]]242 ; RV64I-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[ADD]], [[MULHU]]243 ; RV64I-NEXT: $x10 = COPY [[MUL]]244 ; RV64I-NEXT: $x11 = COPY [[ADD1]]245 ; RV64I-NEXT: PseudoRET implicit $x10, implicit $x11246 %0:gprb(s64) = COPY $x10247 %1:gprb(s64) = COPY $x11248 %2:gprb(s64) = COPY $x12249 %3:gprb(s64) = COPY $x13250 %4:gprb(s64) = G_MUL %0, %2251 %5:gprb(s64) = G_MUL %1, %2252 %6:gprb(s64) = G_MUL %0, %3253 %7:gprb(s64) = G_UMULH %0, %2254 %8:gprb(s64) = G_ADD %5, %6255 %9:gprb(s64) = G_ADD %8, %7256 $x10 = COPY %4(s64)257 $x11 = COPY %9(s64)258 PseudoRET implicit $x10, implicit $x11259 260...261