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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=riscv32 -mattr=+a,+zacas,+zabha -run-pass=instruction-select %s -o - \3# RUN: | FileCheck %s --check-prefixes=RV32IA-ZABHA4 5---6name: cmpxchg_i87legalized: true8regBankSelected: true9 10body: |11 bb.0:12 liveins: $x1013 14 ; RV32IA-ZABHA-LABEL: name: cmpxchg_i815 ; RV32IA-ZABHA: liveins: $x1016 ; RV32IA-ZABHA-NEXT: {{ $}}17 ; RV32IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1018 ; RV32IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x019 ; RV32IA-ZABHA-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 120 ; RV32IA-ZABHA-NEXT: [[AMOCAS_B:%[0-9]+]]:gpr = AMOCAS_B [[COPY1]], [[ADDI]], [[COPY]] :: (load store monotonic (s8))21 ; RV32IA-ZABHA-NEXT: $x10 = COPY [[AMOCAS_B]]22 ; RV32IA-ZABHA-NEXT: PseudoRET implicit $x1023 %0:gpr(p0) = COPY $x1024 %1:gpr(s32) = G_CONSTANT i32 025 %2:gpr(s32) = G_CONSTANT i32 126 %3:gpr(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic (s8))27 $x10 = COPY %3(s32)28 PseudoRET implicit $x1029...30---31name: cmpxchg_i1632legalized: true33regBankSelected: true34 35body: |36 bb.0:37 liveins: $x1038 39 ; RV32IA-ZABHA-LABEL: name: cmpxchg_i1640 ; RV32IA-ZABHA: liveins: $x1041 ; RV32IA-ZABHA-NEXT: {{ $}}42 ; RV32IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1043 ; RV32IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x044 ; RV32IA-ZABHA-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 145 ; RV32IA-ZABHA-NEXT: [[AMOCAS_H:%[0-9]+]]:gpr = AMOCAS_H [[COPY1]], [[ADDI]], [[COPY]] :: (load store monotonic (s16))46 ; RV32IA-ZABHA-NEXT: $x10 = COPY [[AMOCAS_H]]47 ; RV32IA-ZABHA-NEXT: PseudoRET implicit $x1048 %0:gpr(p0) = COPY $x1049 %1:gpr(s32) = G_CONSTANT i32 050 %2:gpr(s32) = G_CONSTANT i32 151 %3:gpr(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic (s16))52 $x10 = COPY %3(s32)53 PseudoRET implicit $x1054...55---56name: cmpxchg_i3257legalized: true58regBankSelected: true59 60body: |61 bb.0:62 liveins: $x1063 64 ; RV32IA-ZABHA-LABEL: name: cmpxchg_i3265 ; RV32IA-ZABHA: liveins: $x1066 ; RV32IA-ZABHA-NEXT: {{ $}}67 ; RV32IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1068 ; RV32IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x069 ; RV32IA-ZABHA-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 170 ; RV32IA-ZABHA-NEXT: [[AMOCAS_W:%[0-9]+]]:gpr = AMOCAS_W [[COPY1]], [[ADDI]], [[COPY]] :: (load store monotonic (s32))71 ; RV32IA-ZABHA-NEXT: $x10 = COPY [[AMOCAS_W]]72 ; RV32IA-ZABHA-NEXT: PseudoRET implicit $x1073 %0:gpr(p0) = COPY $x1074 %1:gpr(s32) = G_CONSTANT i32 075 %2:gpr(s32) = G_CONSTANT i32 176 %3:gpr(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic (s32))77 $x10 = COPY %3(s32)78 PseudoRET implicit $x1079...80---81name: cmpxchg_with_success_i3282legalized: true83regBankSelected: true84 85body: |86 bb.0:87 liveins: $x1088 89 ; RV32IA-ZABHA-LABEL: name: cmpxchg_with_success_i3290 ; RV32IA-ZABHA: liveins: $x1091 ; RV32IA-ZABHA-NEXT: {{ $}}92 ; RV32IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1093 ; RV32IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x094 ; RV32IA-ZABHA-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 195 ; RV32IA-ZABHA-NEXT: [[AMOCAS_W:%[0-9]+]]:gpr = AMOCAS_W [[COPY1]], [[ADDI]], [[COPY]] :: (load store monotonic (s32))96 ; RV32IA-ZABHA-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[AMOCAS_W]], 197 ; RV32IA-ZABHA-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x298 ; RV32IA-ZABHA-NEXT: $x10 = COPY [[AMOCAS_W]]99 ; RV32IA-ZABHA-NEXT: $x11 = COPY [[SLTIU]]100 ; RV32IA-ZABHA-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10101 ; RV32IA-ZABHA-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2102 ; RV32IA-ZABHA-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x10103 ; RV32IA-ZABHA-NEXT: $x10 = COPY [[COPY2]]104 ; RV32IA-ZABHA-NEXT: PseudoRET implicit $x10105 %0:gprb(p0) = COPY $x10106 %1:gprb(s32) = G_CONSTANT i32 0107 %2:gprb(s32) = G_CONSTANT i32 1108 %3:gprb(s32) = G_ATOMIC_CMPXCHG %0(p0), %1, %2 :: (load store monotonic (s32))109 %4:gprb(s32) = G_ICMP intpred(eq), %3(s32), %1110 %5:gprb(s32) = COPY %3(s32)111 ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2112 $x10 = COPY %5(s32)113 $x11 = COPY %4(s32)114 PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10115 ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2116 %6:gprb(s32) = COPY $x10117 $x10 = COPY %6(s32)118 PseudoRET implicit $x10119...120