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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \3# RUN: | FileCheck -check-prefix=RV32I %s4 5---6name: brcond7legalized: true8regBankSelected: true9tracksRegLiveness: true10body: |11 ; RV32I-LABEL: name: brcond12 ; RV32I: bb.0:13 ; RV32I-NEXT: liveins: $x10, $x11, $x1214 ; RV32I-NEXT: {{ $}}15 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1016 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x1117 ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x1218 ; RV32I-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))19 ; RV32I-NEXT: BEQ [[LW]], [[COPY]], %bb.1420 ; RV32I-NEXT: PseudoBR %bb.121 ; RV32I-NEXT: {{ $}}22 ; RV32I-NEXT: bb.1:23 ; RV32I-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))24 ; RV32I-NEXT: BNE [[LW1]], [[COPY]], %bb.1425 ; RV32I-NEXT: PseudoBR %bb.226 ; RV32I-NEXT: {{ $}}27 ; RV32I-NEXT: bb.2:28 ; RV32I-NEXT: [[LW2:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))29 ; RV32I-NEXT: BLT [[LW2]], [[COPY]], %bb.1430 ; RV32I-NEXT: PseudoBR %bb.331 ; RV32I-NEXT: {{ $}}32 ; RV32I-NEXT: bb.3:33 ; RV32I-NEXT: [[LW3:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))34 ; RV32I-NEXT: BGE [[LW3]], [[COPY]], %bb.1435 ; RV32I-NEXT: PseudoBR %bb.436 ; RV32I-NEXT: {{ $}}37 ; RV32I-NEXT: bb.4:38 ; RV32I-NEXT: [[LW4:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))39 ; RV32I-NEXT: BLTU [[LW4]], [[COPY]], %bb.1440 ; RV32I-NEXT: PseudoBR %bb.541 ; RV32I-NEXT: {{ $}}42 ; RV32I-NEXT: bb.5:43 ; RV32I-NEXT: [[LW5:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))44 ; RV32I-NEXT: BGEU [[LW5]], [[COPY]], %bb.1445 ; RV32I-NEXT: PseudoBR %bb.646 ; RV32I-NEXT: {{ $}}47 ; RV32I-NEXT: bb.6:48 ; RV32I-NEXT: [[LW6:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))49 ; RV32I-NEXT: BLT [[COPY]], [[LW6]], %bb.1450 ; RV32I-NEXT: PseudoBR %bb.751 ; RV32I-NEXT: {{ $}}52 ; RV32I-NEXT: bb.7:53 ; RV32I-NEXT: [[LW7:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))54 ; RV32I-NEXT: BGE [[COPY]], [[LW7]], %bb.1455 ; RV32I-NEXT: PseudoBR %bb.856 ; RV32I-NEXT: {{ $}}57 ; RV32I-NEXT: bb.8:58 ; RV32I-NEXT: [[LW8:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))59 ; RV32I-NEXT: BLTU [[COPY]], [[LW8]], %bb.1460 ; RV32I-NEXT: PseudoBR %bb.961 ; RV32I-NEXT: {{ $}}62 ; RV32I-NEXT: bb.9:63 ; RV32I-NEXT: [[LW9:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))64 ; RV32I-NEXT: BGEU [[COPY]], [[LW9]], %bb.1465 ; RV32I-NEXT: PseudoBR %bb.1066 ; RV32I-NEXT: {{ $}}67 ; RV32I-NEXT: bb.10:68 ; RV32I-NEXT: [[LW10:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))69 ; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY2]], 170 ; RV32I-NEXT: BNE [[ANDI]], $x0, %bb.1471 ; RV32I-NEXT: PseudoBR %bb.1172 ; RV32I-NEXT: {{ $}}73 ; RV32I-NEXT: bb.11:74 ; RV32I-NEXT: successors: %bb.14(0x50000000), %bb.12(0x30000000)75 ; RV32I-NEXT: {{ $}}76 ; RV32I-NEXT: [[LW11:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))77 ; RV32I-NEXT: BGE [[LW11]], $x0, %bb.1478 ; RV32I-NEXT: PseudoBR %bb.1279 ; RV32I-NEXT: {{ $}}80 ; RV32I-NEXT: bb.12:81 ; RV32I-NEXT: successors: %bb.14(0x30000000), %bb.13(0x50000000)82 ; RV32I-NEXT: {{ $}}83 ; RV32I-NEXT: [[LW12:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))84 ; RV32I-NEXT: BGE $x0, [[LW12]], %bb.1485 ; RV32I-NEXT: PseudoBR %bb.1386 ; RV32I-NEXT: {{ $}}87 ; RV32I-NEXT: bb.13:88 ; RV32I-NEXT: [[LW13:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))89 ; RV32I-NEXT: {{ $}}90 ; RV32I-NEXT: bb.14:91 ; RV32I-NEXT: PseudoRET92 bb.1:93 liveins: $x10, $x11, $x1294 95 %0:gprb(s32) = COPY $x1096 %1:gprb(p0) = COPY $x1197 %3:gprb(s32) = COPY $x1298 %26:gprb(s32) = G_CONSTANT i32 -199 %29:gprb(s32) = G_CONSTANT i32 1100 %4:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))101 %56:gprb(s32) = G_ICMP intpred(eq), %4(s32), %0102 G_BRCOND %56(s32), %bb.15103 G_BR %bb.2104 105 bb.2:106 %6:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))107 %54:gprb(s32) = G_ICMP intpred(ne), %6(s32), %0108 G_BRCOND %54(s32), %bb.15109 G_BR %bb.3110 111 bb.3:112 %8:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))113 %52:gprb(s32) = G_ICMP intpred(slt), %8(s32), %0114 G_BRCOND %52(s32), %bb.15115 G_BR %bb.4116 117 bb.4:118 %10:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))119 %50:gprb(s32) = G_ICMP intpred(sge), %10(s32), %0120 G_BRCOND %50(s32), %bb.15121 G_BR %bb.5122 123 bb.5:124 %12:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))125 %48:gprb(s32) = G_ICMP intpred(ult), %12(s32), %0126 G_BRCOND %48(s32), %bb.15127 G_BR %bb.6128 129 bb.6:130 %14:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))131 %46:gprb(s32) = G_ICMP intpred(uge), %14(s32), %0132 G_BRCOND %46(s32), %bb.15133 G_BR %bb.7134 135 bb.7:136 %16:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))137 %44:gprb(s32) = G_ICMP intpred(sgt), %16(s32), %0138 G_BRCOND %44(s32), %bb.15139 G_BR %bb.8140 141 bb.8:142 %18:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))143 %42:gprb(s32) = G_ICMP intpred(sle), %18(s32), %0144 G_BRCOND %42(s32), %bb.15145 G_BR %bb.9146 147 bb.9:148 %20:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))149 %40:gprb(s32) = G_ICMP intpred(ugt), %20(s32), %0150 G_BRCOND %40(s32), %bb.15151 G_BR %bb.10152 153 bb.10:154 %22:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))155 %38:gprb(s32) = G_ICMP intpred(ule), %22(s32), %0156 G_BRCOND %38(s32), %bb.15157 G_BR %bb.11158 159 bb.11:160 %24:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))161 %57:gprb(s32) = G_CONSTANT i32 1162 %36:gprb(s32) = G_AND %3, %57163 G_BRCOND %36(s32), %bb.15164 G_BR %bb.12165 166 bb.12:167 successors: %bb.15(0x50000000), %bb.13(0x30000000)168 169 %25:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))170 %35:gprb(s32) = G_ICMP intpred(sgt), %25(s32), %26171 G_BRCOND %35(s32), %bb.15172 G_BR %bb.13173 174 bb.13:175 successors: %bb.15(0x30000000), %bb.14(0x50000000)176 177 %28:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))178 %33:gprb(s32) = G_ICMP intpred(slt), %28(s32), %29179 G_BRCOND %33(s32), %bb.15180 G_BR %bb.14181 182 bb.14:183 %31:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))184 185 bb.15:186 PseudoRET187 188...189