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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \3# RUN: | FileCheck -check-prefix=RV64I %s4 5---6name: brcond7legalized: true8regBankSelected: true9tracksRegLiveness: true10body: |11 ; RV64I-LABEL: name: brcond12 ; RV64I: bb.0:13 ; RV64I-NEXT: liveins: $x10, $x11, $x1214 ; RV64I-NEXT: {{ $}}15 ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1016 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x1117 ; RV64I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x1218 ; RV64I-NEXT: [[LD:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64))19 ; RV64I-NEXT: BEQ [[LD]], [[COPY]], %bb.1420 ; RV64I-NEXT: PseudoBR %bb.121 ; RV64I-NEXT: {{ $}}22 ; RV64I-NEXT: bb.1:23 ; RV64I-NEXT: [[LD1:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64))24 ; RV64I-NEXT: BNE [[LD1]], [[COPY]], %bb.1425 ; RV64I-NEXT: PseudoBR %bb.226 ; RV64I-NEXT: {{ $}}27 ; RV64I-NEXT: bb.2:28 ; RV64I-NEXT: [[LD2:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64))29 ; RV64I-NEXT: BLT [[LD2]], [[COPY]], %bb.1430 ; RV64I-NEXT: PseudoBR %bb.331 ; RV64I-NEXT: {{ $}}32 ; RV64I-NEXT: bb.3:33 ; RV64I-NEXT: [[LD3:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64))34 ; RV64I-NEXT: BGE [[LD3]], [[COPY]], %bb.1435 ; RV64I-NEXT: PseudoBR %bb.436 ; RV64I-NEXT: {{ $}}37 ; RV64I-NEXT: bb.4:38 ; RV64I-NEXT: [[LD4:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64))39 ; RV64I-NEXT: BLTU [[LD4]], [[COPY]], %bb.1440 ; RV64I-NEXT: PseudoBR %bb.541 ; RV64I-NEXT: {{ $}}42 ; RV64I-NEXT: bb.5:43 ; RV64I-NEXT: [[LD5:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64))44 ; RV64I-NEXT: BGEU [[LD5]], [[COPY]], %bb.1445 ; RV64I-NEXT: PseudoBR %bb.646 ; RV64I-NEXT: {{ $}}47 ; RV64I-NEXT: bb.6:48 ; RV64I-NEXT: [[LD6:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64))49 ; RV64I-NEXT: BLT [[COPY]], [[LD6]], %bb.1450 ; RV64I-NEXT: PseudoBR %bb.751 ; RV64I-NEXT: {{ $}}52 ; RV64I-NEXT: bb.7:53 ; RV64I-NEXT: [[LD7:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64))54 ; RV64I-NEXT: BGE [[COPY]], [[LD7]], %bb.1455 ; RV64I-NEXT: PseudoBR %bb.856 ; RV64I-NEXT: {{ $}}57 ; RV64I-NEXT: bb.8:58 ; RV64I-NEXT: [[LD8:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64))59 ; RV64I-NEXT: BLTU [[COPY]], [[LD8]], %bb.1460 ; RV64I-NEXT: PseudoBR %bb.961 ; RV64I-NEXT: {{ $}}62 ; RV64I-NEXT: bb.9:63 ; RV64I-NEXT: [[LD9:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64))64 ; RV64I-NEXT: BGEU [[COPY]], [[LD9]], %bb.1465 ; RV64I-NEXT: PseudoBR %bb.1066 ; RV64I-NEXT: {{ $}}67 ; RV64I-NEXT: bb.10:68 ; RV64I-NEXT: [[LD10:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64))69 ; RV64I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY2]], 170 ; RV64I-NEXT: BNE [[ANDI]], $x0, %bb.1471 ; RV64I-NEXT: PseudoBR %bb.1172 ; RV64I-NEXT: {{ $}}73 ; RV64I-NEXT: bb.11:74 ; RV64I-NEXT: successors: %bb.14(0x50000000), %bb.12(0x30000000)75 ; RV64I-NEXT: {{ $}}76 ; RV64I-NEXT: [[LD11:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64))77 ; RV64I-NEXT: BGE [[LD11]], $x0, %bb.1478 ; RV64I-NEXT: PseudoBR %bb.1279 ; RV64I-NEXT: {{ $}}80 ; RV64I-NEXT: bb.12:81 ; RV64I-NEXT: successors: %bb.14(0x30000000), %bb.13(0x50000000)82 ; RV64I-NEXT: {{ $}}83 ; RV64I-NEXT: [[LD12:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64))84 ; RV64I-NEXT: BGE $x0, [[LD12]], %bb.1485 ; RV64I-NEXT: PseudoBR %bb.1386 ; RV64I-NEXT: {{ $}}87 ; RV64I-NEXT: bb.13:88 ; RV64I-NEXT: [[LD13:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64))89 ; RV64I-NEXT: {{ $}}90 ; RV64I-NEXT: bb.14:91 ; RV64I-NEXT: PseudoRET92 bb.1:93 liveins: $x10, $x11, $x1294 95 %0:gprb(s64) = COPY $x1096 %1:gprb(p0) = COPY $x1197 %3:gprb(s64) = COPY $x1298 %26:gprb(s64) = G_CONSTANT i64 -199 %29:gprb(s64) = G_CONSTANT i64 1100 %4:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64))101 %56:gprb(s64) = G_ICMP intpred(eq), %4(s64), %0102 G_BRCOND %56(s64), %bb.15103 G_BR %bb.2104 105 bb.2:106 %6:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64))107 %54:gprb(s64) = G_ICMP intpred(ne), %6(s64), %0108 G_BRCOND %54(s64), %bb.15109 G_BR %bb.3110 111 bb.3:112 %8:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64))113 %52:gprb(s64) = G_ICMP intpred(slt), %8(s64), %0114 G_BRCOND %52(s64), %bb.15115 G_BR %bb.4116 117 bb.4:118 %10:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64))119 %50:gprb(s64) = G_ICMP intpred(sge), %10(s64), %0120 G_BRCOND %50(s64), %bb.15121 G_BR %bb.5122 123 bb.5:124 %12:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64))125 %48:gprb(s64) = G_ICMP intpred(ult), %12(s64), %0126 G_BRCOND %48(s64), %bb.15127 G_BR %bb.6128 129 bb.6:130 %14:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64))131 %46:gprb(s64) = G_ICMP intpred(uge), %14(s64), %0132 G_BRCOND %46(s64), %bb.15133 G_BR %bb.7134 135 bb.7:136 %16:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64))137 %44:gprb(s64) = G_ICMP intpred(sgt), %16(s64), %0138 G_BRCOND %44(s64), %bb.15139 G_BR %bb.8140 141 bb.8:142 %18:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64))143 %42:gprb(s64) = G_ICMP intpred(sle), %18(s64), %0144 G_BRCOND %42(s64), %bb.15145 G_BR %bb.9146 147 bb.9:148 %20:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64))149 %40:gprb(s64) = G_ICMP intpred(ugt), %20(s64), %0150 G_BRCOND %40(s64), %bb.15151 G_BR %bb.10152 153 bb.10:154 %22:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64))155 %38:gprb(s64) = G_ICMP intpred(ule), %22(s64), %0156 G_BRCOND %38(s64), %bb.15157 G_BR %bb.11158 159 bb.11:160 %24:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64))161 %57:gprb(s64) = G_CONSTANT i64 1162 %36:gprb(s64) = G_AND %3, %57163 G_BRCOND %36(s64), %bb.15164 G_BR %bb.12165 166 bb.12:167 successors: %bb.15(0x50000000), %bb.13(0x30000000)168 169 %25:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64))170 %35:gprb(s64) = G_ICMP intpred(sgt), %25(s64), %26171 G_BRCOND %35(s64), %bb.15172 G_BR %bb.13173 174 bb.13:175 successors: %bb.15(0x30000000), %bb.14(0x50000000)176 177 %28:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64))178 %33:gprb(s64) = G_ICMP intpred(slt), %28(s64), %29179 G_BRCOND %33(s64), %bb.15180 G_BR %bb.14181 182 bb.14:183 %31:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64))184 185 bb.15:186 PseudoRET187 188...189