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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \3# RUN: | FileCheck -check-prefix=RV32I %s4 5---6name: virt_to_phys7legalized: true8regBankSelected: true9tracksRegLiveness: true10body: |11 bb.0.entry:12 13 ; RV32I-LABEL: name: virt_to_phys14 ; RV32I: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 115 ; RV32I-NEXT: $x10 = COPY [[ADDI]]16 ; RV32I-NEXT: PseudoRET implicit $x1017 %0:gprb(s32) = G_CONSTANT i32 118 $x10 = COPY %0(s32)19 PseudoRET implicit $x1020 21...22---23name: phys_to_phys24legalized: true25regBankSelected: true26tracksRegLiveness: true27body: |28 bb.0.entry:29 liveins: $x10, $x1130 31 ; RV32I-LABEL: name: phys_to_phys32 ; RV32I: liveins: $x10, $x1133 ; RV32I-NEXT: {{ $}}34 ; RV32I-NEXT: $x10 = COPY $x1135 ; RV32I-NEXT: PseudoRET implicit $x1036 $x10 = COPY $x1137 PseudoRET implicit $x1038 39...40---41name: virt_to_virt42legalized: true43regBankSelected: true44tracksRegLiveness: true45body: |46 bb.0.entry:47 48 ; RV32I-LABEL: name: virt_to_virt49 ; RV32I: PseudoRET50 %0:gprb(s32) = G_CONSTANT i32 151 %1:gprb(s32) = COPY %0(s32)52 PseudoRET53 54...55---56name: phys_to_virt57legalized: true58regBankSelected: true59tracksRegLiveness: true60body: |61 bb.0.entry:62 liveins: $x1063 64 ; RV32I-LABEL: name: phys_to_virt65 ; RV32I: liveins: $x1066 ; RV32I-NEXT: {{ $}}67 ; RV32I-NEXT: PseudoRET68 %0:gprb(s32) = COPY $x1069 PseudoRET70 71...72