23 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=instruction-select \3# RUN: -simplify-mir -verify-machineinstrs %s -o - \4# RUN: | FileCheck -check-prefix=RV32I %s5 6---7name: ctlz_s328legalized: true9regBankSelected: true10body: |11 bb.0.entry:12 ; RV32I-LABEL: name: ctlz_s3213 ; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x1014 ; RV32I-NEXT: [[CLZ:%[0-9]+]]:gpr = CLZ [[COPY]]15 ; RV32I-NEXT: $x10 = COPY [[CLZ]]16 ; RV32I-NEXT: PseudoRET implicit $x1017 %0:gprb(s32) = COPY $x1018 %1:gprb(s32) = G_CTLZ %019 $x10 = COPY %1(s32)20 PseudoRET implicit $x1021 22...23