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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=instruction-select \3# RUN: -simplify-mir -verify-machineinstrs %s -o - \4# RUN: | FileCheck -check-prefix=RV64I %s5 6---7name: ctlz_s328legalized: true9regBankSelected: true10body: |11 bb.0.entry:12 ; RV64I-LABEL: name: ctlz_s3213 ; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x1014 ; RV64I-NEXT: [[CLZW:%[0-9]+]]:gpr = CLZW [[COPY]]15 ; RV64I-NEXT: $x10 = COPY [[CLZW]]16 ; RV64I-NEXT: PseudoRET implicit $x1017 %0:gprb(s64) = COPY $x1018 %1:gprb(s64) = G_CLZW %019 $x10 = COPY %1(s64)20 PseudoRET implicit $x1021 22...23---24name: ctlz_s6425legalized: true26regBankSelected: true27body: |28 bb.0.entry:29 ; RV64I-LABEL: name: ctlz_s6430 ; RV64I: [[CLZ:%[0-9]+]]:gpr = CLZ [[CLZ]]31 ; RV64I-NEXT: $x10 = COPY [[CLZ]]32 ; RV64I-NEXT: PseudoRET implicit $x1033 %0:gprb(s64) = COPY $x1034 %1:gprb(s64) = G_CTLZ %135 $x10 = COPY %1(s64)36 PseudoRET implicit $x1037 38...39