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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 32# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=instruction-select \3# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s4# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=instruction-select \5# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s6 7---8name: half_imm9legalized: true10regBankSelected: true11body: |12 bb.1:13 ; CHECK-LABEL: name: half_imm14 ; CHECK: [[LUI:%[0-9]+]]:gpr = LUI 415 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], 58416 ; CHECK-NEXT: [[FMV_H_X:%[0-9]+]]:fpr16 = FMV_H_X [[ADDI]]17 ; CHECK-NEXT: $f10_h = COPY [[FMV_H_X]]18 ; CHECK-NEXT: PseudoRET implicit $f10_h19 %0:fprb(s16) = G_FCONSTANT half 0xH424820 $f10_h = COPY %0(s16)21 PseudoRET implicit $f10_h22 23...24---25name: half_imm_op26legalized: true27regBankSelected: true28body: |29 bb.1:30 liveins: $f10_h31 32 ; CHECK-LABEL: name: half_imm_op33 ; CHECK: liveins: $f10_h34 ; CHECK-NEXT: {{ $}}35 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h36 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1537 ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADDI]], 1038 ; CHECK-NEXT: [[FMV_H_X:%[0-9]+]]:fpr16 = FMV_H_X [[SLLI]]39 ; CHECK-NEXT: [[FADD_H:%[0-9]+]]:fpr16 = nofpexcept FADD_H [[COPY]], [[FMV_H_X]], 740 ; CHECK-NEXT: $f10_h = COPY [[FADD_H]]41 ; CHECK-NEXT: PseudoRET implicit $f10_h42 %0:fprb(s16) = COPY $f10_h43 %1:fprb(s16) = G_FCONSTANT half 1.000000e+0044 %2:fprb(s16) = G_FADD %0, %145 $f10_h = COPY %2(s16)46 PseudoRET implicit $f10_h47 48...49---50name: half_positive_zero51legalized: true52regBankSelected: true53body: |54 bb.1:55 liveins: $x1056 57 ; CHECK-LABEL: name: half_positive_zero58 ; CHECK: liveins: $x1059 ; CHECK-NEXT: {{ $}}60 ; CHECK-NEXT: [[FMV_H_X:%[0-9]+]]:fpr16 = FMV_H_X $x061 ; CHECK-NEXT: $f10_h = COPY [[FMV_H_X]]62 ; CHECK-NEXT: PseudoRET implicit $f10_h63 %1:fprb(s16) = G_FCONSTANT half 0.000000e+0064 $f10_h = COPY %1(s16)65 PseudoRET implicit $f10_h66 67...68---69name: half_negative_zero70legalized: true71regBankSelected: true72body: |73 bb.1:74 liveins: $x1075 76 ; CHECK-LABEL: name: half_negative_zero77 ; CHECK: liveins: $x1078 ; CHECK-NEXT: {{ $}}79 ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 104856880 ; CHECK-NEXT: [[FMV_H_X:%[0-9]+]]:fpr16 = FMV_H_X [[LUI]]81 ; CHECK-NEXT: $f10_h = COPY [[FMV_H_X]]82 ; CHECK-NEXT: PseudoRET implicit $f10_h83 %1:fprb(s16) = G_FCONSTANT half -0.000000e+0084 $f10_h = COPY %1(s16)85 PseudoRET implicit $f10_h86 87...88