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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 32# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=instruction-select \3# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,RV324# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=instruction-select \5# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,RV646 7---8name: float_imm9legalized: true10regBankSelected: true11body: |12 bb.1:13 ; CHECK-LABEL: name: float_imm14 ; CHECK: [[LUI:%[0-9]+]]:gpr = LUI 26331315 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], -3716 ; CHECK-NEXT: [[FMV_W_X:%[0-9]+]]:fpr32 = FMV_W_X [[ADDI]]17 ; CHECK-NEXT: $f10_f = COPY [[FMV_W_X]]18 ; CHECK-NEXT: PseudoRET implicit $f10_f19 %0:fprb(s32) = G_FCONSTANT float 0x400921FB6000000020 $f10_f = COPY %0(s32)21 PseudoRET implicit $f10_f22 23...24---25name: float_imm_op26legalized: true27regBankSelected: true28body: |29 bb.1:30 liveins: $f10_f31 32 ; CHECK-LABEL: name: float_imm_op33 ; CHECK: liveins: $f10_f34 ; CHECK-NEXT: {{ $}}35 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f36 ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 26009637 ; CHECK-NEXT: [[FMV_W_X:%[0-9]+]]:fpr32 = FMV_W_X [[LUI]]38 ; CHECK-NEXT: [[FADD_S:%[0-9]+]]:fpr32 = nofpexcept FADD_S [[COPY]], [[FMV_W_X]], 739 ; CHECK-NEXT: $f10_f = COPY [[FADD_S]]40 ; CHECK-NEXT: PseudoRET implicit $f10_f41 %0:fprb(s32) = COPY $f10_f42 %1:fprb(s32) = G_FCONSTANT float 1.000000e+0043 %2:fprb(s32) = G_FADD %0, %144 $f10_f = COPY %2(s32)45 PseudoRET implicit $f10_f46 47...48---49name: float_positive_zero50legalized: true51regBankSelected: true52body: |53 bb.1:54 liveins: $x1055 56 ; CHECK-LABEL: name: float_positive_zero57 ; CHECK: liveins: $x1058 ; CHECK-NEXT: {{ $}}59 ; CHECK-NEXT: [[FMV_W_X:%[0-9]+]]:fpr32 = FMV_W_X $x060 ; CHECK-NEXT: $f10_f = COPY [[FMV_W_X]]61 ; CHECK-NEXT: PseudoRET implicit $f10_f62 %1:fprb(s32) = G_FCONSTANT float 0.000000e+0063 $f10_f = COPY %1(s32)64 PseudoRET implicit $f10_f65 66...67---68name: float_negative_zero69legalized: true70regBankSelected: true71body: |72 bb.1:73 liveins: $x1074 75 ; CHECK-LABEL: name: float_negative_zero76 ; CHECK: liveins: $x1077 ; CHECK-NEXT: {{ $}}78 ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 52428879 ; CHECK-NEXT: [[FMV_W_X:%[0-9]+]]:fpr32 = FMV_W_X [[LUI]]80 ; CHECK-NEXT: $f10_f = COPY [[FMV_W_X]]81 ; CHECK-NEXT: PseudoRET implicit $f10_f82 %1:fprb(s32) = G_FCONSTANT float -0.000000e+0083 $f10_f = COPY %1(s32)84 PseudoRET implicit $f10_f85 86...87---88name: double_imm89legalized: true90regBankSelected: true91body: |92 bb.1:93 ; RV32-LABEL: name: double_imm94 ; RV32: [[LUI:%[0-9]+]]:gpr = LUI 26229095 ; RV32-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], 50796 ; RV32-NEXT: [[LUI1:%[0-9]+]]:gpr = LUI 34515597 ; RV32-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI [[LUI1]], -74498 ; RV32-NEXT: [[BuildPairF64Pseudo:%[0-9]+]]:fpr64 = BuildPairF64Pseudo [[ADDI1]], [[ADDI]]99 ; RV32-NEXT: $f10_d = COPY [[BuildPairF64Pseudo]]100 ; RV32-NEXT: PseudoRET implicit $f10_d101 ;102 ; RV64-LABEL: name: double_imm103 ; RV64: [[LUI:%[0-9]+]]:gpr = LUI 512104 ; RV64-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], 1169105 ; RV64-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADDI]], 15106 ; RV64-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI [[SLLI]], -299107 ; RV64-NEXT: [[SLLI1:%[0-9]+]]:gpr = SLLI [[ADDI1]], 14108 ; RV64-NEXT: [[ADDI2:%[0-9]+]]:gpr = ADDI [[SLLI1]], 1091109 ; RV64-NEXT: [[SLLI2:%[0-9]+]]:gpr = SLLI [[ADDI2]], 12110 ; RV64-NEXT: [[ADDI3:%[0-9]+]]:gpr = ADDI [[SLLI2]], -744111 ; RV64-NEXT: [[FMV_D_X:%[0-9]+]]:fpr64 = FMV_D_X [[ADDI3]]112 ; RV64-NEXT: $f10_d = COPY [[FMV_D_X]]113 ; RV64-NEXT: PseudoRET implicit $f10_d114 %0:fprb(s64) = G_FCONSTANT double 0x400921FB54442D18115 $f10_d = COPY %0(s64)116 PseudoRET implicit $f10_d117 118...119---120name: double_imm_op121legalized: true122regBankSelected: true123body: |124 bb.1:125 liveins: $f10_d126 127 ; RV32-LABEL: name: double_imm_op128 ; RV32: liveins: $f10_d129 ; RV32-NEXT: {{ $}}130 ; RV32-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d131 ; RV32-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 261888132 ; RV32-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0133 ; RV32-NEXT: [[BuildPairF64Pseudo:%[0-9]+]]:fpr64 = BuildPairF64Pseudo [[COPY1]], [[LUI]]134 ; RV32-NEXT: [[FADD_D:%[0-9]+]]:fpr64 = nofpexcept FADD_D [[COPY]], [[BuildPairF64Pseudo]], 7135 ; RV32-NEXT: $f10_d = COPY [[FADD_D]]136 ; RV32-NEXT: PseudoRET implicit $f10_d137 ;138 ; RV64-LABEL: name: double_imm_op139 ; RV64: liveins: $f10_d140 ; RV64-NEXT: {{ $}}141 ; RV64-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d142 ; RV64-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1023143 ; RV64-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADDI]], 52144 ; RV64-NEXT: [[FMV_D_X:%[0-9]+]]:fpr64 = FMV_D_X [[SLLI]]145 ; RV64-NEXT: [[FADD_D:%[0-9]+]]:fpr64 = nofpexcept FADD_D [[COPY]], [[FMV_D_X]], 7146 ; RV64-NEXT: $f10_d = COPY [[FADD_D]]147 ; RV64-NEXT: PseudoRET implicit $f10_d148 %0:fprb(s64) = COPY $f10_d149 %1:fprb(s64) = G_FCONSTANT double 1.000000e+00150 %2:fprb(s64) = G_FADD %0, %1151 $f10_d = COPY %2(s64)152 PseudoRET implicit $f10_d153 154...155---156name: double_positive_zero157legalized: true158regBankSelected: true159body: |160 bb.1:161 liveins: $x10162 163 ; RV32-LABEL: name: double_positive_zero164 ; RV32: liveins: $x10165 ; RV32-NEXT: {{ $}}166 ; RV32-NEXT: [[FCVT_D_W:%[0-9]+]]:fpr64 = FCVT_D_W $x0, 0167 ; RV32-NEXT: $f10_d = COPY [[FCVT_D_W]]168 ; RV32-NEXT: PseudoRET implicit $f10_d169 ;170 ; RV64-LABEL: name: double_positive_zero171 ; RV64: liveins: $x10172 ; RV64-NEXT: {{ $}}173 ; RV64-NEXT: [[FMV_D_X:%[0-9]+]]:fpr64 = FMV_D_X $x0174 ; RV64-NEXT: $f10_d = COPY [[FMV_D_X]]175 ; RV64-NEXT: PseudoRET implicit $f10_d176 %1:fprb(s64) = G_FCONSTANT double 0.000000e+00177 $f10_d = COPY %1(s64)178 PseudoRET implicit $f10_d179 180...181---182name: double_negative_zero183legalized: true184regBankSelected: true185body: |186 bb.1:187 liveins: $x10188 189 ; RV32-LABEL: name: double_negative_zero190 ; RV32: liveins: $x10191 ; RV32-NEXT: {{ $}}192 ; RV32-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 524288193 ; RV32-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0194 ; RV32-NEXT: [[BuildPairF64Pseudo:%[0-9]+]]:fpr64 = BuildPairF64Pseudo [[COPY]], [[LUI]]195 ; RV32-NEXT: $f10_d = COPY [[BuildPairF64Pseudo]]196 ; RV32-NEXT: PseudoRET implicit $f10_d197 ;198 ; RV64-LABEL: name: double_negative_zero199 ; RV64: liveins: $x10200 ; RV64-NEXT: {{ $}}201 ; RV64-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1202 ; RV64-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADDI]], 63203 ; RV64-NEXT: [[FMV_D_X:%[0-9]+]]:fpr64 = FMV_D_X [[SLLI]]204 ; RV64-NEXT: $f10_d = COPY [[FMV_D_X]]205 ; RV64-NEXT: PseudoRET implicit $f10_d206 %1:fprb(s64) = G_FCONSTANT double -0.000000e+00207 $f10_d = COPY %1(s64)208 PseudoRET implicit $f10_d209 210...211