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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=riscv32 -mattr=+d,+zfh -run-pass=instruction-select %s -o - \3# RUN: | FileCheck %s4# RUN: llc -mtriple=riscv64 -mattr=+d,+zfh -run-pass=instruction-select %s -o - \5# RUN: | FileCheck %s6 7---8name: fp_store_f329legalized: true10regBankSelected: true11selected: false12tracksRegLiveness: true13body: |14 bb.0:15 liveins: $x10, $f10_f16 17 ; CHECK-LABEL: name: fp_store_f3218 ; CHECK: liveins: $x10, $f10_f19 ; CHECK-NEXT: {{ $}}20 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1021 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f10_f22 ; CHECK-NEXT: FSW [[COPY1]], [[COPY]], 0 :: (store (s32))23 ; CHECK-NEXT: PseudoRET24 %0:gprb(p0) = COPY $x1025 %1:fprb(s32) = COPY $f10_f26 G_STORE %1(s32), %0(p0) :: (store (s32))27 PseudoRET28 29...30---31name: fp_store_f6432legalized: true33regBankSelected: true34tracksRegLiveness: true35body: |36 bb.0:37 liveins: $x10, $f10_d38 39 ; CHECK-LABEL: name: fp_store_f6440 ; CHECK: liveins: $x10, $f10_d41 ; CHECK-NEXT: {{ $}}42 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1043 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f10_d44 ; CHECK-NEXT: FSD [[COPY1]], [[COPY]], 0 :: (store (s64))45 ; CHECK-NEXT: PseudoRET46 %0:gprb(p0) = COPY $x1047 %1:fprb(s64) = COPY $f10_d48 G_STORE %1(s64), %0(p0) :: (store (s64))49 PseudoRET50 51...52---53name: fp_load_f3254legalized: true55regBankSelected: true56tracksRegLiveness: true57body: |58 bb.0:59 liveins: $x1060 61 ; CHECK-LABEL: name: fp_load_f3262 ; CHECK: liveins: $x1063 ; CHECK-NEXT: {{ $}}64 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1065 ; CHECK-NEXT: [[FLW:%[0-9]+]]:fpr32 = FLW [[COPY]], 0 :: (load (s32))66 ; CHECK-NEXT: $f10_f = COPY [[FLW]]67 ; CHECK-NEXT: PseudoRET implicit $f10_f68 %0:gprb(p0) = COPY $x1069 %1:fprb(s32) = G_LOAD %0(p0) :: (load (s32))70 $f10_f = COPY %1(s32)71 PseudoRET implicit $f10_f72 73...74---75name: fp_load_f6476legalized: true77regBankSelected: true78tracksRegLiveness: true79body: |80 bb.0:81 liveins: $x1082 83 ; CHECK-LABEL: name: fp_load_f6484 ; CHECK: liveins: $x1085 ; CHECK-NEXT: {{ $}}86 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1087 ; CHECK-NEXT: [[FLD:%[0-9]+]]:fpr64 = FLD [[COPY]], 0 :: (load (s64))88 ; CHECK-NEXT: $f10_d = COPY [[FLD]]89 ; CHECK-NEXT: PseudoRET implicit $f10_d90 %0:gprb(p0) = COPY $x1091 %1:fprb(s64) = G_LOAD %0(p0) :: (load (s64))92 $f10_d = COPY %1(s64)93 PseudoRET implicit $f10_d94 95...96---97name: fp_store_f1698legalized: true99regBankSelected: true100selected: false101tracksRegLiveness: true102body: |103 bb.0:104 liveins: $x10, $f10_h105 106 ; CHECK-LABEL: name: fp_store_f16107 ; CHECK: liveins: $x10, $f10_h108 ; CHECK-NEXT: {{ $}}109 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10110 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f10_h111 ; CHECK-NEXT: FSH [[COPY1]], [[COPY]], 0 :: (store (s16))112 ; CHECK-NEXT: PseudoRET113 %0:gprb(p0) = COPY $x10114 %1:fprb(s16) = COPY $f10_h115 G_STORE %1(s16), %0(p0) :: (store (s16))116 PseudoRET117 118...119---120name: fp_load_f16121legalized: true122regBankSelected: true123tracksRegLiveness: true124body: |125 bb.0:126 liveins: $x10127 128 ; CHECK-LABEL: name: fp_load_f16129 ; CHECK: liveins: $x10130 ; CHECK-NEXT: {{ $}}131 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10132 ; CHECK-NEXT: [[FLH:%[0-9]+]]:fpr16 = FLH [[COPY]], 0 :: (load (s16))133 ; CHECK-NEXT: $f10_h = COPY [[FLH]]134 ; CHECK-NEXT: PseudoRET implicit $f10_h135 %0:gprb(p0) = COPY $x10136 %1:fprb(s16) = G_LOAD %0(p0) :: (load (s16))137 $f10_h = COPY %1(s16)138 PseudoRET implicit $f10_h139 140...141