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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=instruction-select \3# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s4 5---6name: fptosi_s32_s167legalized: true8regBankSelected: true9tracksRegLiveness: true10body: |11 bb.1:12 liveins: $f10_h13 14 ; CHECK-LABEL: name: fptosi_s32_s1615 ; CHECK: liveins: $f10_h16 ; CHECK-NEXT: {{ $}}17 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h18 ; CHECK-NEXT: [[FCVT_W_H:%[0-9]+]]:gpr = nofpexcept FCVT_W_H [[COPY]], 119 ; CHECK-NEXT: $x10 = COPY [[FCVT_W_H]]20 ; CHECK-NEXT: PseudoRET implicit $x1021 %0:fprb(s16) = COPY $f10_h22 %1:gprb(s32) = G_FPTOSI %0(s16)23 $x10 = COPY %1(s32)24 PseudoRET implicit $x1025 26...27---28name: fptoui_s32_s1629legalized: true30regBankSelected: true31tracksRegLiveness: true32body: |33 bb.1:34 liveins: $f10_h35 36 ; CHECK-LABEL: name: fptoui_s32_s1637 ; CHECK: liveins: $f10_h38 ; CHECK-NEXT: {{ $}}39 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h40 ; CHECK-NEXT: [[FCVT_WU_H:%[0-9]+]]:gpr = nofpexcept FCVT_WU_H [[COPY]], 141 ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_H]]42 ; CHECK-NEXT: PseudoRET implicit $x1043 %0:fprb(s16) = COPY $f10_h44 %1:gprb(s32) = G_FPTOUI %0(s16)45 $x10 = COPY %1(s32)46 PseudoRET implicit $x1047 48...49